I
參數(shù)資料
型號(hào): KSZ8041NLJ TR
廠(chǎng)商: Micrel Inc
文件頁(yè)數(shù): 31/43頁(yè)
文件大小: 0K
描述: TXRX PHY 10/100 3.3V 32MLF
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: MII,RMII
電源電壓: 3.135 V ~ 3.465 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán),32-MLF?
供應(yīng)商設(shè)備封裝: 32-MLF?(5x5)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱(chēng): 576-3625-6
2012 Microchip Technology Inc.
DS25118C-page 37
MCP47DA1
5.2.5
STOP BIT
The Stop bit (see Figure 5-6) indicates the end of the
I2C data transfer sequence. The Stop bit is defined as
the SDA signal rising when the SCL signal is “High”.
A Stop bit resets the I2C interface of the other devices.
FIGURE 5-6:
Stop Condition Receive or
Transmit Mode.
5.2.6
CLOCK STRETCHING
“Clock Stretching” is something that the secondary
device can do, to allow additional time to “respond” to
the “data” that has been received.
The MCP47DA1 will not stretch the clock signal (SCL)
since memory read accesses occur fast enough.
5.2.7
ABORTING A TRANSMISSION
If any part of the I2C transmission does not meet the
command format, it is aborted. This can be intentionally
accomplished with a START or STOP condition. This is
done so that noisy transmissions (usually an extra
START or STOP condition) are aborted before they
corrupt the device.
5.2.8
IGNORING AN I2C TRANSMISSION
AND “FALLING OFF” THE BUS
The MCP47DA1 expects to receive entire, valid I2C
commands and will assume any command not defined
as a valid command is due to a bus corruption, and will
enter a passive high condition on the SDA signal. All
signals will be ignored until the next valid START con-
dition and CONTROL BYTE are received.
FIGURE 5-7:
Typical 16-bit I2C Waveform Format.
FIGURE 5-8:
I2C Data States and Bit Sequence.
SCL
SDA A / A
P
1st
SDA
SCL
S
2nd 3rd 4th 5th 6th 7th 8th
P
A/A
Bit Bit
Bit Bit Bit Bit Bit Bit
1st 2nd 3rd 4th 5th 6th 7th 8th A/A
Bit Bit
Bit Bit Bit Bit Bit
Bit
SCL
SDA
START
Condition
STOP
Condition
Data allowed
to change
Data or
A valid
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