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參數(shù)資料
| 型號： | KSC7333 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Digital Image Stabilization and Digital Zoom Processor |
| 中文描述： | 數(shù)字圖像穩(wěn)定和數(shù)碼變焦處理器 |
| 文件頁數(shù)： | 12/44頁 |
| 文件大?。?/td> | 284K |
| 代理商： | KSC7333 |
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KS7333
DATA SHEET
12
PICTURE-IN-PICTURE BLOCK
This block uses the AD-converted S1S2 format image as an 8-bit input, divides it into Y/C, and finds the typical
value for each Y/C through low pass filtering. The filtered Y/C signal is synthesized into S1S2 format and stored
in real time, 2 fields at a time, using the SDRAM. The compression-stored image signal is overlayed on the real
image using the location value which comes from the MICOM control value.
1/16 compression
4-line, 4-pixel sampling
1 field memory (16M SDRAM) used (2 fields stored)
TEMPORAL IIR FILTER BLOCK
This block receives the image's output signal, stores it in SDRAM through DPCM compression, reads the stored
signal in real time, then restores it. The restored image signal is divided into Y/C, and it goes through the 255-
step linear interpolation to be synthesized into S1S2 format. This synthesized image signal and the zoom output
are
3-D interpolated using the sub-pixel information output by the motion detection and the zoom.
DPCM compression/restoration
1 field memory (16M SDRAM) used (2 fields stored)
3D-interpolation
2-line interpolation of Y signal
2-line selection of C signal
MICOM INTERFACE BLOCK
This block which interfaces with the external MICOM, selects this system's internal register and receives internal
characteristic factors as feedback. Its basic signals are SMI, SMO, SCLK, and SCSN. The first byte of the input
data is the register's address, and the data which follows is valid only when SCSN is high.
Address control method
122-byte input register
70-byte output register
Internal register initializing feature by reset
Possible to control both read only by R/W flag and read & write simultaneity mode.
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