參數(shù)資料
型號(hào): KSC7333
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Digital Image Stabilization and Digital Zoom Processor
中文描述: 數(shù)字圖像穩(wěn)定和數(shù)碼變焦處理器
文件頁(yè)數(shù): 13/44頁(yè)
文件大?。?/td> 284K
代理商: KSC7333
DATA SHEET
KS7333
13
SYNC GENERATION BLOCK
This block generates the image's horizontal/vertical count information using the sync signal from the Timing
Generator (TG) as the standard. It uses DVC, HIGH, PAL, and AP_ADJ (start point adjustment) from the system
MICOM to generate the SP (Start Point) information by getting height value, image start point, image width and
generate HD, VD, and FLD (FIELD) signals.
Internal vertical counter (VCNT: line counter)
Internal horizontal counter (HCNT: pixel counter)
Internal field signal (FLD)
OSD SIGNAL CONTROL BLOCK
This block controls the 1-bit output of the OSD signal using the internal register value. The form of the output
signal is the center position of the PIP box and AF, and the testing graph of the motion vector.
Motion test vector graph output
PIP box output
AF center position output
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