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參數(shù)資料
| 型號： | KS8805B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Universal Programmable PLL(通用可編程鎖相環(huán)) |
| 中文描述： | 通用可編程鎖相環(huán)（通用可編程鎖相環(huán)） |
| 文件頁數(shù)： | 7/26頁 |
| 文件大?。?/td> | 171K |
| 代理商： | KS8805B |
KS8805B UNIVERSAL PROGRAMMABLE PLL
- Flow chart and timing diagram of the control Register [ PMC (Bit 7) = 1 (High)]
When programming the control register, PMC (bit 7) data and EN data must be set to ‘1’.
- Input data format of control register programming
The following timing diagrams show how to set the input data of the CLK, AUXDI, DI and EN pin, and what is
the timing margin each other. EN - Data set - up time and CLK - EN delay time should be Min. 50 ns, and data
hold time need to be Min. 100ns.
In addition to that time, operating wait time in register setting is Min. 200 ns.
PMC
= 1
COC
TM
AUX DI EN
fMCUS
PWD
TX
PWD
RX
PWD
REF
DI
EN
CLK
MSB
LSB
Control register setting
Next sequence
> 50 ns
> 100 ns
> 50 ns
> 200 ns
> 50 ns
DI
CLK
EN
Operating
flow
> 50 ns
COC
TM
AUXDI
fMCUS
PWD
TX
PWD
REF
PMC
PWD
RX
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