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參數(shù)資料
| 型號： | KS8805B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Universal Programmable PLL(通用可編程鎖相環(huán)) |
| 中文描述： | 通用可編程鎖相環(huán)（通用可編程鎖相環(huán)） |
| 文件頁數(shù)： | 10/26頁 |
| 文件大?。?/td> | 171K |
| 代理商： | KS8805B |
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KS8805B UNIVERSAL PROGRAMMABLE PLL
- Input data format in reference register programming
The following timing diagram show how to program the input data format in reference register setting, and how much is the
timing margin each other.
EN - Data set - up time and CLK - EN delay time should be Min. 50ns, and data hold time need to be Min. 100ns. In addition
to that time, operating wait time in register setting is Min. 200 ns.
PLL TX / RX count register Programming
There are two type programming method in TX / RX 16 Bits divider setting.
The one is 3 - Pin used programming and the other is 4 - Pin used programming. If the 4 - Pin used programming method is
applied for the faster operating time, AUXDI Pin is added.
When the TX / RX count register is setting, EN Pin state is ‘low’.
- Normal Programming [AUXDIEN = ‘Low’ (0)]
When the three pin interface method is applied, AUXDIEN (Bit 4) operating state must be ‘Low’ in control register
Reference register setting
Next sequence
> 50 ns
> 100 ns
> 50 ns
> 200 ns
> 50 ns
DI
CLK
EN
> 50 ns
AUXREN
TXTS
REFS1
PMC
TXRS
REFD
REFS2
AREFD
TX 16 - bit Count Data
Receiver 16-bit Count Data
DI
EN
CLK
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