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參數(shù)資料
| 型號： | KS8805B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Universal Programmable PLL(通用可編程鎖相環(huán)) |
| 中文描述： | 通用可編程鎖相環(huán)（通用可編程鎖相環(huán)） |
| 文件頁數(shù)： | 4/26頁 |
| 文件大?。?/td> | 171K |
| 代理商： | KS8805B |
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KS8805B UNIVERSAL PROGRAMMABLE PLL
PIN DESCRIPTION
Pin No
Symbol
Description
9
RIF
Input terminal of RX channel counter
Usually, AC coupled output signal of VCO loop is introduced and the
Minimum input signal level is 300mVp-p at 60 MHz
10
PDR
There are 3 - kind output signal states in PDR pin.
- If fRX > fREF (fRX is leading), the output is negative pulse state
- If fRX < fREF (fRX is lagging), the output is positive pulse state
- If fRX = fREF (the same phase), the output is high impedance state
11
PWD
RX
This output terminal offers the state of internal RX channel counter operation.
If this pin state is high, internal RX channel counter is operating in power saving
mode. So, this pin can be used in appling the power switch on / off control.
12
VDD
Power supply input terminal
13
PWD
TX
This output terminal offers the state of internal TX channel counter operation.
If this pin state is high, internal TX channel counter is operating in power saving
mode. So, this pin can be used in appling the power switch on / off control.
14
TIF
Input terminal of TX channel counter
Usually, AC coupled output signal of VCO loop is introduced and the Minimum
input signal level is 300mVp-p at 60 MHz
15
PDT
There are 3 - kind output signal states in PDT pin.
- If fTX > fREF (fTX is leading), the output is negative pulse state
- If fTX < fREF (fTX is lagging), the output is positive pulse state
- If fTX = fREF (the same phase), the output is high impedance state
16
LDT
Output terminal of lock detection waveforms
This output pin is internally connected with TX - loop. High output state in
LDT pin indicates out of internal operation.
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