KS8695PX Micrel System Level Hardware Interfaces Clock and Reset JTAG WAN Ethernet PHY LAN Ethernet PHY A" />
參數(shù)資料
型號： KS8695PX-EVAL
廠商： Micrel Inc
文件頁數(shù)： 9/40頁
文件大?。?/td> 0K
描述： BOARD EVAL EXPERIMENT KS8695PX
標準包裝： 1
相關(guān)產(chǎn)品： KS8695PXA3-ND - IC ARM9 W/MMU 5PORT 289-PBGA
KS8695PX-ND - IC SWITCH 10/100 1PORT 289PBGA
其它名稱： 576-1004
September 2005
17
M9999-091605
KS8695PX
Micrel
System Level Hardware Interfaces
Clock and Reset
JTAG
WAN Ethernet
PHY
LAN Ethernet
PHY
Advanced
Memory
Interface
UART
GPIO
PHY LED
Drivers
Factory Test
Power and
Ground
KS8695P
PCI
Figure 3. System Level Interfaces
At the system level the KS8695PX features the following interfaces:
Clock interface for crystal or external oscillator
JTAG development interface
One WAN Ethernet physical interface
Four LAN Ethernet physical interfaces
PHY LED drivers
One high-speed UART interface
Sixteen GPIO pins
33MHz, 32-bit PCI interface supporting one external master
Advanced memory interface
– Programmable synchronous bus rate
– Programmable asynchronous interface timing
– Independently programmable data bus width for static and synchronous memory
– Glueless connection to SDRAM
– Glueless connection to ash memory or ROM
Factory test
Power and ground
Conguration Pins
The following pins are sampled as input during reset
Conguration
Pin Name
Pin #
Setting
Bank0 Flash Data Width
B0SIZE[1:0]
E14, E15
‘00’= reserved
‘01’ = byte wide
‘10’ = half word wide (16 bits)
‘11’ = word wide (32 bits)
WRSTO Polarity
EROEN/WRSTPLS
U17
‘0’ = active high
‘1’ = active low
CPU Clock Select
URTSN/CPUCLKSEL
M15
‘0’ = normal mode (PLL)
'1’ = bypass internal PLL
PCI Bridge Mode
PBMS
D3
‘0’ = guest bridge mode
‘1’ = host bridge mode
CPUCLKSEL
URTSN/CPUCLKSEL
M15
‘0’ = normal operation
‘1’ = factory reserved
Debug Enable
UDTRN/DBGENN
N15
‘0’ = factory reserved
Table 1. Conguration Pins
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