KS8695PX Micrel Memory Interface The KS8695PX has a glueless interface for SDRAM and static memory, i.e. " />
參數(shù)資料
型號: KS8695PX-EVAL
廠商: Micrel Inc
文件頁數(shù): 13/40頁
文件大?。?/td> 0K
描述: BOARD EVAL EXPERIMENT KS8695PX
標(biāo)準(zhǔn)包裝: 1
相關(guān)產(chǎn)品: KS8695PXA3-ND - IC ARM9 W/MMU 5PORT 289-PBGA
KS8695PX-ND - IC SWITCH 10/100 1PORT 289PBGA
其它名稱: 576-1004
M9999-091605
20
September 2005
KS8695PX
Micrel
Memory Interface
The KS8695PX has a glueless interface for SDRAM and
static memory, i.e. ROM, SRAM, and Flash. It supports up
to two banks of static memory (Figure 7), up to two banks of
SDRAM (Figure 8), and three banks of external I/O (Figure
9). The total address space for the KS8695PX is 64MB.
This includes SDRAM, static memory, external I/O, and the
KS8695PX's own 64KB of register space.
The memory interface for the SDRAM and static memory has
a special automatic address mapping feature. This allows the
designer to connect address bit 0 on the memory to ADDR[0]
ontheKS8695PXandaddressbit1onthememorytoADDR[1]
on the memory, regardless of whether the designer is trying
to achieve word, half word, or byte addressing.
The KS8695PX memory controller performs the address
mapping internally. This permits the designer to use the
maximum amount of address bits, instead of losing one
or two bits because of address mapping. For external I/O,
however, the designer still needs to take care of the address
mapping (see Figure 9).
KS8695P
Byte Wide
Static Memory
ADDR0
ADDR1
ADDR[21:2]
A0
A1
A[21:2]
DATA[7:0]
D[7:0]
8
20
OE
WE
CE
RCSN0
EROEN
ERWEN0
KS8695P
Half Word Wide
Static Memory
ADDR0
ADDR1
ADDR[21:2]
A0
A1
A[21:2]
DATA[15:0]
D[15:0]
16
20
OE
WE
CE
RCSN0
EROEN
ERWEN0
BYTE
VDD
Figure 7. Static Memory Interface Examples
SDOCLK
SDCKE
DATA[31..0]
ADDR[11..0]
SDRASN
SDCASN
SDQM[3..0]
SDWEN
KS8695P
SDRAM
4M x 32
CLK
CKE
CS#
WE#
CAS#
RAS#
A[11..0]
DQ[31..0]
SDCSN0
DQM[3..0]
ADDR[21..20]
BA[1..0]
32
12
2
4
SDICLK
SDOCLK
SDCKE
DATA[15..0]
ADDR[12..0]
SDRASN
SDCASN
SDQM0
SDWEN
KS8695P
SDRAM
16M x 16
CLK
CKE
CS#
WE#
CAS#
RAS#
A[12..0]
DQ[15..0]
SDCSN0
LDQM
ADDR[21..20]
BA[1..0]
16
13
2
SDICLK
SDQM1
UDQM
Half Word Wide
Word Wide
Figure 8. SDRAM Interface Examples
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