
KS0119 Data Sheet
MULTIMEDIA VIDEO
ELECTRONICS
PAGE 8 OF 50
070595
1. GENERAL DESCRIPTION
The KS0119 is a digital NTSC encoder combined with basic RAM-DAC functions. It is designed to be a high
performance, cost effective NTSC or PC display driver. The chip consists of a two way Color Space Converter,
which is capable of supporting almost all the popular input formats pertaining to PC video, graphics, or image
compression/decompression. The chip contains signal processing blocks to enhance image quality and reduce
artifacts due to sampling. It provides image manipulation facilities such as masking, mixing, hue control, and color
lookup tables to create special effects. It includes a programmable Timing Generator to generate the
synchronization signals and color burst for different display monitors.
1.1. Application
The KS0119 is a versatile chip, which can be used for many application such as NTSC encoding, YUV DAC, RAM
DAC, Gamma correction, mixing, and VGA overlay. CK27 must be used for NTSC encoder, whereas CKV must be
used for the others. It is recommended that the unused clock input pin be tied to a static state.
1.2. Power On Default
The KS0119 can be configured for two power-on default states: one for NTSC video encoding and the other for VGA
overlay application. For the latter the MRQST/MODE pin must be pulled up so the KS0119 defaults to sync
pass
through
mode and Channel A is set to support 8-bit pseudo color format after power up. In this mode, the KS0119
functions as a RAM-DAC. The internal video timing generator is disabled; the horizontal and vertical syncs are delay
compensated for the video path delay and passed to the sync output pins. The sync pass through mode is
recommended for VGA overlay application.
1.3. Operation Mode
The KS0119 can be configured to operate either in master mode or slave mode. In the master mode the encoder
uses the parameter stored in the CRT control registers to generate all the video timings and outputs synchronizing
signals (refer to “VIDEO OPERATIONAL TIMING” on page 18). In the slave mode the encoder synchronize the
internal pixel counter on the falling edge of AV
,
and line counter on the rising edge or VBLK. The sync outputs, HSYN
and VSYN, waveform can be modified if sync pass through is disabled (
SYNCPT
=0). Table 2 shows the registers
related to the sync generation.
Table 1: Power On Default State
Power On MRQST/MODE Pin State
Operations
Channel A Input Format SYNCPT Clock Source
0
NTSC encoding 4:2:2 YCbCr
0
CK27
1
VGA overlay
8 bit pseudo color
1
CKV
Table 2: Sync Output Generation
MASTER
SLAVE
Control Registers
HSYN, VSYN
Video Output Port Sync
Polarity
Input Sync Polarity Control
CRT Control Registers
Comments
MSTR
=1
Internally generated
Active low
MSTR
=0,
SYNCPT
=1
Pass through
Inverted AV and VBLK
MSTR
=0,
SYNCPT
=0
Regenerated
Active low
N/A
Index Registers 70 - 79h
VSP
,
HSP
Recommend for VGA
overlay application