參數(shù)資料
型號: KS0119
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Multimedia Video(帶傳統(tǒng)RAM-DAC功能的NTSC編碼器)
中文描述: 多媒體視頻(帶傳統(tǒng)的RAM - DAC的功能的NTSC制式編碼器)
文件頁數(shù): 13/47頁
文件大?。?/td> 311K
代理商: KS0119
KS0119 Data Sheet
MULTIMEDIA VIDEO
ELECTRONICS
PAGE 13 OF 50
070595
2.2.1. Index Keying
If channel A’s input format is 2, 3, 4, 5, or 6, Index Keying can be used for mixing. Channel A’s inputs are first
compared with the contents in the two 8 bit
TEMPLATE
registers (
TMPLB
,
TMPLA
). The results are then filtered by
the
MASK
registers (
MSKB
,
MSKA
) and ANDed together to generate the key signal. If the input is 8 or 15 bits wide,
the unused bits are automatically masked out. Figure 4 shows the logic operation involved in Index Keying.
Figure 4. Index Keying Generation
2.2.2. Chroma Keying
If channel A’s input is YCbCr format, Chroma Keying can be used for mixing. A rectangular area is specified in the
Cb-Cr space (Figure 5). If Channel A’s Cb/Cr values fall within this area, Channel B’s video will be displayed. In this
mode,
TMPLA
and
TMPLB
specify the lower and upper Cb, respectively, and
MSKA
and
MSKB
specify the lower
and upper Cr, respectively, in the Cb-Cr space. Note that Cb and Cr are binary offset numbers with 128
corresponding to zero intensity, 0 and 255 corresponding to maximum intensity.
Figure 5. Cb-Cr Chroma Keying
2.2.3. Window Keying
A rectangular key window is specified in X-Y coordinates in the active display area. If window mixing is enabled and
the
OUTSD
bit of the
Mixing
Control
register is 0, Channel B is displayed inside the window, and Channel A is
outside the window. The converse is true if the
OUTSD
bit is 1. If both the Chroma and Window Keyings are enabled,
the
OUTSD
bit specifies where the Chroma Keying will be applied: 0 inside the window and 1 outside the window.
The 8 msb’s of the four 10 bit coordinate registers, Window Horizontal Start Address, Window Horizontal End
Address, Window Vertical Start Address and Window Vertical End Address, are stored in the
WHS
,
WHE
,
WVS
and
WVE
registers, respectively, while the 2 lsb bits are stored in the
WHV
register. The four msb registers are double
clocked, and synchronized to the
WVE
write. A write to the
WVE
register will transfer the four msb registers’
contents, concatenated with their corresponding lsb’s, to the respective final address registers. Modifying the msb
T
E
M
P
L
A
T
E
M
A
S
K
C
H
A
N
N
E
L
A
INDEX
KEY
Cb
Cr
128,128
128,255
255,128
CCIR Color
Key
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