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參數(shù)資料
| 型號： | KMC8610VT1333JB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 82/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC HOST PROCESS 1333MHZ 783-PBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC86xx |
| 處理器類型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.333GHz |
| 電壓： | 1.025V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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Hardware Design Considerations
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
83
3.10
Guidelines for High-Speed Interface Termination
3.10.1
SerDes Interface
The high-speed SerDes interface can be disabled through the POR input cfg_io_ports[0:2] and through the DEVDISR register
in software. If a SerDes port is disabled through the POR input the user can not enable it through the DEVDISR register in
software. However, if a SerDes port is enabled through the POR input the user can disable it through the DEVDISR register in
software. Disabling a SerDes port through software should be done on a temporary basis. Power is always required for the
SerDes interface, even if the port is disabled through either mechanism. Table 61 describes the possible enabled/disabled
scenarios for a SerDes port. The termination recommendations must be followed for each port.
If the high-speed SerDes port requires complete or partial termination, the unused pins should be terminated as described in this
section.
The following pins must be left unconnected (floating):
SDn_TX[7:0]
The following pins must be connected to GND:
SDn_RX[7:0]
SDn_REF_CLK
SDn_REF_CLK
For other directions on reserved or no-connects pins, see Section 1, “Pin Assignments and Reset States.”
Table 61. SerDes Port Enabled/Disabled Configurations
Disabled through POR input
Enabled through POR input
Enabled through DEVDISR
SerDes port is disabled (and cannot
be enabled through DEVDISR)
Complete termination required
(Reference clock not required
SerDes port is enabled
Partial termination may be required1
(Reference clock is required)
1 Partial termination when a SerDes port is enabled through both POR input and DEVDISR is determined by the
SerDes port mode. If port 1 is in x4 PCI Express mode, no termination is required because all pins are being
used. If port 1 is in x1/x2 PCI Express mode, termination is required on the unused pins. If port 2 is in x8 PCI
Express mode, no termination is required because all pins are being used. If port 1 is in x1/x2/x4 PCI Express
mode, termination is required on the unused pins.
Disabled through DEVDISR
SerDes port is disabled (through
POR input)
Complete termination required
(Reference clock not required)
SerDes port is disabled after software
disables port
Same termination requirements as
when the port is enabled through POR
input2
(Reference clock is required)
2 If a SerDes port is enabled through the POR input and then disabled through DEVDISR, no hardware changes
are required. Termination of the SerDes port should follow what is required when the port is enabled through
both POR input and DEVDISR. See Note 1 for more information.
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