參數(shù)資料
型號(hào)： KMC8610VT1333JB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 53/96頁(yè)
文件大?。?/td> 0K
描述： IC HOST PROCESS 1333MHZ 783-PBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.333GHz
電壓： 1.025V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤(pán)
Electrical Characteristics
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
57
— For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since
the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver
operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has
its common mode voltage set to SGND. Each signal wire of the differential inputs is allowed to swing below and
above the command mode voltage (SGND). Figure 32 shows the SerDes reference clock input requirement for
AC-coupled connection scheme.
Single-ended mode
— The reference clock can also be single-ended. The SDn_REF_CLK input amplitude (single-ended swing) must be
between 400 and 800 mV peak-peak (from Vmin to Vmax) with SDn_REF_CLK either left unconnected or tied to
ground.
—The SDn_REF_CLK input average voltage must be between 200 and 400 mV. Figure 33 shows the SerDes
reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC- or AC-coupled
externally. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused
phase (SDn_REF_CLK) through the same source impedance as the clock input (SDn_REF_CLK) in use.
Figure 31. Differential Reference Clock Input DC Requirements (External DC-Coupled)
Figure 32. Differential Reference Clock Input DC Requirements (External AC-Coupled)
Figure 33. Single-Ended Reference Clock Input DC Requirements
SD
n_REF_CLK
SD
n_REF_CLK
Vmax < 800 mV
Vmin > 0V
100 mV < Vcm < 400 mV
200 mV < Input Amplitude or Differential Peak < 800 mV
SD
n_REF_CLK
SD
n_REF_CLK
SD
n_REF_CLK
Vcm
200mV < Input Amplitude or Differential Peak < 800 mV
Vmax < Vcm + 400 mV
Vmin > Vcm – 400 mV
SD
n_REF_CLK
SD
n_REF_CLK
400 mV < SD
n_REF_CLK Input Amplitude < 800 mV
0 V
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