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參數(shù)資料
| 型號： | KMC8113TVT4800V |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 19/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 300/400MHZ 431FCPGA |
| 標準包裝： | 2 |
| 系列： | StarCore |
| 類型： | SC140 內(nèi)核 |
| 接口： | 以太網(wǎng)，I²C，TDM，UART |
| 時鐘速率： | 400MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 1.436MB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.10V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 431-BFBGA，F(xiàn)CBGA |
| 供應商設(shè)備封裝： | 431-FCPBGA（20x20） |
| 包裝： | 托盤 |
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MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 1
Electrical Characteristics
Freescale Semiconductor
26
2.5.6
DSI Timing
The timings in the following sections are based on a 20 pF capacitive load.
2.5.6.1
DSI Asynchronous Mode
Figure 13. DMA Signals
Table 18. DSI Asynchronous Mode Timing
No.
Characteristics
Min
Max
Unit
100
Attributes1 set-up time before strobe (HWBS[n]) assertion
1.5
—
ns
101
Attributes1 hold time after data strobe deassertion
1.3
—
ns
102
Read/Write data strobe deassertion width:
DCR[HTAAD] = 1
— Consecutive access to the same DSI
— Different device with DCR[HTADT] = 01
— Different device with DCR[HTADT] = 10
— Different device with DCR[HTADT] = 11
DCR[HTAAD] = 0
1.8 + TREFCLK
5 + TREFCLK
5 + (1.5
× TREFCLK)
5 + (2.5
× TREFCLK)
1.8 + TREFCLK
—
ns
103
Read data strobe deassertion to output data high impedance
—
8.5
ns
104
Read data strobe assertion to output data active from high impedance
2.0
—
ns
105
Output data hold time after read data strobe deassertion
2.2
—
ns
106
Read/Write data strobe assertion to HTA active from high impedance
2.2
—
ns
107
Output data valid to HTA assertion
3.2
—
ns
108
Read/Write data strobe assertion to HTA valid2
—7.4
ns
109
Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 0, HTA at end of access released at logic 0)
—6.5
ns
110
Read/Write data strobe deassertion to output HTA deassertion.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1)
—6.5
ns
111
Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1
DCR[HTADT] = 01
DCR[HTADT] = 10
DCR[HTADT] = 11
—
5 + TREFCLK
5 + (1.5
× TREFCLK)
5 + (2.5
× TREFCLK)
ns
112
Read/Write data strobe assertion width
1.8 + TREFCLK
—ns
201
Host data input set-up time before write data strobe deassertion
1.0
—
ns
202
Host data input hold time after write data strobe deassertion
1.7
—
ns
Notes:
1.
Attributes refers to the following signals: HCS, HA[11–29], HCID[0–4], HDST, HRW, HRDS, and HWBSn.
2.
This specification is tested in dual-strobe mode. Timing in single-strobe mode is guaranteed by design.
3.
All values listed in this table are tested or guaranteed by design.
REFCLK
DREQ
DONE
DACK/DONE/DRACK
37
38
40
39
41
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