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參數(shù)資料
| 型號(hào)： | KMC68MH360ZQ25VL |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 9/14頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MPU QUICC 25MHZ 357-PBGA |
| 標(biāo)準(zhǔn)包裝： | 2 |
| 系列： | M683xx |
| 處理器類(lèi)型： | M683xx 32-位 |
| 速度： | 25MHz |
| 電壓： | 5V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 357-BBGA |
| 供應(yīng)商設(shè)備封裝： | 357-PBGA（25x25） |
| 包裝： | 托盤(pán) |
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QUICC ARCHITECTURE OVERVIEW
The QUICC is 32-bit controller that is an extension of other members of the Freescale M68300 family. Like
other members of the M68300 family, the QUICC incorporates the intermodule bus (IMB). (The MC68302 is
an exception, having an M68000 bus on chip.) The IMB provides a common interface for all modules of the
M68300 family, which allows Freescale to develop new devices more quickly by using the library of existing
modules. Although the IMB definition always included an option for an on-chip 32-bit bus, the QUICC is the
first device to implement this option.
The QUICC is comprised of three modules: the CPU32+ core, the SIM60, and the CPM. Each module
utilizes the 32-bit IMB. The MC68360 QUICC block diagram is shown in Figure 1.
EXTERNAL
BUS
INTERFACE
SYSTEM
PROTECTION
SIM 60
CPU32+
CORE
IMB (32 BIT)
RISC
CONTROLLER
SYSTEM
I/F
2.5-KBYTE
DUAL-PORT
RAM
DRAM
CONTROLLER
AND
CHIP SELECTS
CPM
PERIODIC
TIMER
CLOCK
GENERATION
OTHER
FEATURES
BREAKPOINT
LOGIC
JTAG
COMMUNICATIONS PROCESSOR
FOUR
GENERAL-
PURPOSE
TIMERS
INTERRUPT
CONTROLLER
OTHER
FEATURES
TIMER SLOT
ASSIGNER
SEVEN
SERIAL
CHANNELS
TWO
IDMAs
FOURTEEN SERIAL
DMAs
F
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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