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| 型號(hào)： | KMC68MH360ZQ25VL |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 1/14頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MPU QUICC 25MHZ 357-PBGA |
| 標(biāo)準(zhǔn)包裝： | 2 |
| 系列： | M683xx |
| 處理器類(lèi)型： | M683xx 32-位 |
| 速度： | 25MHz |
| 電壓： | 5V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 357-BBGA |
| 供應(yīng)商設(shè)備封裝： | 357-PBGA（25x25） |
| 包裝： | 托盤(pán) |
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by MC68360D
MC68360
Product Brief
MC68360 QUad Integrated Communication
Controller (QUICC)
INTRODUCTION
The MC68360 QUad Integrated Communication Controller (QUICC
) is a versatile one-chip integrated
microprocessor and peripheral combination that can be used in a variety of controller applications. It
particularly excels in communications activities. The QUICC (pronounced “quick”) can be described as a
next-generation MC68302 with higher performance in all areas of device operation, increased flexibility,
major extensions in capability, and higher integration. The term "quad" comes from the fact that there are
four serial communications controllers (SCCs) on the device; however, there are actually seven serial
channels: four SCCs, two serial management controllers (SMCs), and one serial peripheral interface (SPI).
QUICC Key Features
The following list summarizes the key MC68360 QUICC features:
CPU32+ Processor (4.5 MIPS at 25 MHz)
— 32-Bit Version of the CPU32 Core (Fully Compatible with the CPU32)
— Background Debug Mode
— Byte-Misaligned Addressing
Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)
Up to 32 Address Lines (At Least 28 Always Available)
Complete Static Design (0–25-MHz Operation)
Slave Mode To Disable CPU32+ (Allows Use with External Processors)
— Multiple QUICCs Can Share One System Bus (One Master)
— MC68040 Companion Mode Allows QUICC To Be an MC68040 Companion
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For More Information On This Product,
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Freescale Semiconductor
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