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參數(shù)資料
| 型號(hào)： | KM718V990 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx18 Synchronous SRAM(512Kx18位同步靜態(tài) RAM) |
| 中文描述： | 512Kx18同步SRAM（512Kx18位同步靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 3/17頁 |
| 文件大小： | 365K |
| 代理商： | KM718V990 |
PRELIMINARY
KM718V990
256Kx36 & 512Kx18 Synchronous SRAM
- 3 -
Rev 0.4
Sep. 1998
KM736V890
PIN CONFIGURATION
(TOP VIEW)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A
0
- A
17
ADV
ADSP
ADSC
CLK
CS
1
CS
2
CS
2
WEx(x=a,b,c,d)
OE
GW
BW
ZZ
LBO
Address Inputs
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
32,33,34,35,36,37,43
44,45,46,47,48,49,50
81,82,99,100
83
84
85
89
98
97
92
93,94,95,96
86
88
87
64
31
V
DD
V
SS
N.C.
DQa
0
~a
7
DQb
0
~b
7
DQc
0
~c
7
DQd
0
~d
7
DQPa~P
d
V
DDQ
V
SSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Output Power Supply
(+3.3V)
Output Ground
15,41,65,91
17,40,67,90
14,16,38,39,42,66
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin
TQFP
(20mm x 14mm)
KM736V890(256Kx36)
DQPc
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
N.C.
V
DD
N.C.
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
DQPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
N.C.
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa
1
9
9
9
9
9
9
9
9
9
9
8
8
8
8
8
8
8
8
A
6
A
7
C
1
C
2
W
W
W
W
C
2
V
D
V
S
C
G
B
O
A
A
A
A
8
8
A
9
5
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
A
1
A
1
A
1
A
1
A
1
A
1
A
1
N
V
D
V
S
N
N
A
0
A
1
A
2
A
3
A
4
A
5
3
L
A
1
NOTE :
1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
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