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參數(shù)資料
| 型號： | KM718V687 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64Kx18 Synchronous SRAM(64Kx18位同步靜態(tài) RAM) |
| 中文描述： | 64Kx18同步SRAM（64Kx18位同步靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 342K |
| 代理商： | KM718V687 |
PRELIMINARY
KM718V687
64Kx18 Synchronous SRAM
- 4 -
Rev 1.0
May 1997
FUNCTION DESCRIPTION
The KM718V687 is a synchronous SRAM designed to support the burst address accessing sequence of the Pentium and Power PC
based microprocessor. All inputs(with the exception of OE, LBO and ZZ) are sampled on rising clock edges.
The start and duration of the burst access is controlled by ADSP, ADSC, ADV and Chip Select pins.
When ZZ is pulled HIGH, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to LOW, the SRAM normally operates after 2 cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(or ADSC) using the new external address clocked into the on-chip address register when both
GW and BW are high or when BW is low and both WEa and WEb are high, When ADSP is sampled low, the chip selects are sam-
pled active, and the output buffer is enabled with OE, the data of cell array accessed by the current address are projected to the out-
put pins.
Write cycles are also initiated with ADSP(or ADSC) and are differentiated into two kinds of operations; All byte write operation and
individual byte write operation.
All byte write occurs by enabling GW(in dependent of BW and WEx.), and individual byte write is performed only when GW is High
and BW is Low. In KM718V687, A 64Kx18 organization, WEa controls DQa
0
~ DQa
7
and DQPa, WEb controls DQb
0
~ DQb
7
and
DQPb.
CS
1
is used to enable the device and conditions internal use of ADSP and is sampled only when a new external address is loaded.
ADV is ignored at the clock edge when ADSP is asserted, but can be sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when ADV is sampled low.
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. And when this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE
(Interleaved Burst)
Case 1
A
1
A
0
First Address
0
0
1
1
1
BURST SEQUENCE
(Linear Burst)
LBO PIN
HIGH
Case 2
Case 3
Case 4
A
1
0
0
1
1
A
0
1
0
1
0
A
1
1
1
0
0
A
0
0
1
0
1
A
1
1
1
0
0
A
0
1
0
1
0
Fourth Address
0
1
0
NOTE : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
LBO PIN
LOW
Case 1
Case 2
Case 3
Case 4
A
1
0
0
1
1
A
0
0
1
0
1
A
1
0
1
1
0
A
0
1
0
1
0
A
1
1
1
0
0
A
0
0
1
0
1
A
1
1
0
0
1
A
0
1
0
1
0
First Address
Fourth Address
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2)
Operation
ZZ
OE
I/O Status
Sleep Mode
H
X
High-Z
Read
L
L
DQ
L
H
High-Z
Write
L
X
Din, High-Z
Deselected
L
X
High-Z
NOTE
1. X means "Don
′
t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must
be disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current
does not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
TRUTH TABLES
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