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參數(shù)資料
| 型號(hào)： | KM718V687 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64Kx18 Synchronous SRAM(64Kx18位同步靜態(tài) RAM) |
| 中文描述： | 64Kx18同步SRAM（64Kx18位同步靜態(tài)內(nèi)存） |
| 文件頁(yè)數(shù)： | 2/15頁(yè) |
| 文件大?。?/td> | 342K |
| 代理商： | KM718V687 |
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PRELIMINARY
KM718V687
64Kx18 Synchronous SRAM
- 2 -
Rev 1.0
May 1997
FAST ACCESS TIMES
Parameter
Symbol
-8
-9
-10
Unit
Cycle Time
t
CYC
12
12
15
ns
Clock Access Time
t
CD
8.5
9
10
ns
Output Enable Access Time
t
OE
4
4
5
ns
64Kx18-Bit Synchronous Burst SRAM
FEATURES
The KM718V687 is a 1,179,648 bits Synchronous Static Ran-
dom Access Memory designed to support zero wait state per-
formance for advanced Pentium and Power PC based system.
And with CS
1
high, ADSP is blocked to control signal.
It is organized as 64K words of 18bits. And it integrates address
and control registers, a 2-bit burst address counter and high
output drive circuitry onto a single integrated circuit for reduced
components counts implementation of high performance cache
RAM applications.
Write cycles are internally self-timed and synchronous.
The self-timed write feature eliminates complex off chip write
pulse shaping logic, simplifying the cache design and further
reducing the component count.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system
′
s burst sequence and are controlled by the burst
address advance(ADV) input.
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The KM718V687 is implemented with SAMSUNG
′
s high perfor-
mance CMOS technology and is available in a 100pin TQFP
package. Multiple power and ground pins are utilized to mini-
mize ground bounce.
GENERAL DESCRIPTION
LOGIC BLOCK DIAGRAM
Synchronous Operation.
On-Chip Address Counter.
Write Self-Timed Cycle.
On-Chip Address and Control Registers.
Single 3.3V
±
5% Power Supply.
5V Tolerant Inputs except I/O Pins.
Byte Writable Function.
Global Write Enable Controls a full bus-width write.
Power Down State via ZZ Signal.
Asynchronous Output Enable Control.
ADSP, ADSC, ADV Burst Control Pins.
LBO Pin allows a choice of either a interleaved burst or a
linear burst.
Three Chip Enables for simple depth expansion with No Data
Contention.
TTL-Level Three-State Output.
100-TQFP-1420A
CLK
LBO
ADV
ADSC
ADSP
CS
1
CS
2
CS
2
GW
BW
WEa
WEb
OE
ZZ
DQa
0
~ DQb
7
DQPa, DQPb
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
64Kx18
MEMORY
ARRAY
ADDRESS
REGISTER
CONTROL
LOGIC
OUTPUT
BUFFER
DATA-IN
REGISTER
C
R
C
R
A
′
0
~
A
′
1
A
0
~ A
1
A
2
~A
15
A
0
~A
15
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