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參數(shù)資料
| 型號： | KM718B86 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64Kx18-Bit Synchronous SRAM(64Kx18位同步靜態(tài) RAM) |
| 中文描述： | 64Kx18位同步SRAM（64Kx18位同步靜態(tài)內存） |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 274K |
| 代理商： | KM718B86 |
PRELIMINARY
KM718B86
64Kx18 Synchronous SRAM
- 6 -
Rev 1.1
April 1997
AC TIMING CHARACTERISTICS
(T
A
=0 to 70
°
C, V
CC
=5V
±
5%)
NOTE : All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS
is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. Both chip
selects must be active whenever ADSC or ADSP is sampled low in order for this device to remain enabled.
Parameter
Symbol
KM718B86-8
Min
KM718B86-9
Min
KM718B86-10
Min
KM718B86-12
Min
Unit
Max
Max
Max
Max
Cycle Time
Clock Access Time
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
t
CYC
t
CD
t
OE
t
LZC
t
OH
15
-
-
6
3
-
8
5
-
-
15
-
-
6
3
-
9
5
-
-
17
-
-
6
3
-
20
-
-
6
3
-
ns
ns
ns
ns
ns
10
5
-
-
12
6
-
-
t
LZOE
0
-
0
-
0
-
0
-
ns
Output Enable High to Output High-Z
t
HZOE
2
5
2
5
2
5
2
5
ns
Clock High to Output High-Z
Clock High Pulse Width
Clock Low Pulse Width
t
HZC
t
CH
-
5
6
-
-
5
6
-
-
5
6
-
-
6
6
-
ns
ns
t
CL
5
-
5
-
5
-
6
-
ns
Address Setup to Clock High
Address Status Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High
Address/Advance Setup to Clock
t
AS
t
SS
t
DS
t
WS
2.5
2.5
2.5
2.5
-
-
-
-
2.5
2.5
2.5
2.5
-
-
-
-
2.5
2.5
2.5
2.5
-
-
-
-
2.5
2.5
2.5
2.5
-
-
-
-
ns
ns
ns
ns
t
ADVS
2.5
-
2.5
-
2.5
-
2.5
-
ns
Chip Select Setup to Clock High
Address Hold from Clock High
Address Status Hold from Clock High
t
CSS
t
AH
2.5
0.5
-
-
2.5
0.5
-
-
2.5
0.5
-
-
2.5
0.5
-
-
ns
ns
t
SH
0.5
-
0.5
-
0.5
-
0.5
-
ns
Data Hold from Clock High
Write Hold from Clock High
Address Advance Hold from Clock
t
DH
t
WH
0.5
0.5
-
-
0.5
0.5
-
-
0.5
0.5
-
-
0.5
0.5
-
-
ns
ns
t
ADVH
0.5
-
0.5
-
0.5
-
0.5
-
ns
Chip Select Hold from Clock High
t
CSH
0.5
-
0.5
-
0.5
-
0.5
-
ns
Output Load(A)
Output Load(B)
(for t
LZC,
t
LZOE,
t
HZOE
& t
HZC
)
Dout
Z0=50
RL=50
VL=1.5V
Dout
255
5pF*
+3.3V
480
* Including Scope and Jig Capacitance
Fig. 1
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| KM718FV4021 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18 Synchronous Pipelined SRAM |
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| KM718FV4021H-6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18 Synchronous Pipelined SRAM |
| KM718FV4021H-7 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18 Synchronous Pipelined SRAM |
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