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參數(shù)資料
| 型號： | KM718B86 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64Kx18-Bit Synchronous SRAM(64Kx18位同步靜態(tài) RAM) |
| 中文描述： | 64Kx18位同步SRAM（64Kx18位同步靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 274K |
| 代理商： | KM718B86 |
PRELIMINARY
KM718B86
64Kx18 Synchronous SRAM
- 3 -
Rev 1.1
April 1997
FUNCTION DESCRIPTION
The KM718B86 is a synchronous SRAM designed to support the burst address accessing sequence of the Power microprocessor. All
inputs(with the exception of OE) are sampled on rising clock edges. The start and duration of the burst access is controlled by ADSP and
ADSC. The accesses are enabled with the chip select signals and output enable. Wait states are inserted into the access with ADV.
Read cycles are initiated with ADSP(regardless of LW, UW and ADSC) using the new external address clocked into the on-chip address
register whenever ADSP is sample low, The chip selects are sampled active, and the output buffer is enabled with OE, ADV is ignored
on the clock edge that samples ADSP asserted, but is sampled on the next and subsequent clock edges. The address is increased inter-
nally for the next access of the burst when LW, UW is sampled HIGH and ADV is sampled low.
Write cycles are performed by disabling the output buffers with OE and asserting LW, UW. LW, UW is ignored on the clock edge that
sampled ADSP low, but is sampled on the next and subsequent clock edges. The output buffers are disabled when LW, UW is sampled
low (regardless of OE). Data is clocked into the input register when LW, UW is sampled low. The address increases internally to the next
address of burst, if both LW, UW and ADV are sampled Low. Individual byte write cycles are performed sampling low only one byte write
enable signals(LW or LU)and LW controls I/O
0
~I/O
7
and UW controls I/O
8
~I/O
17
.
Read or write cycles (depending on LW, LU)may also be initiated with ADSC, instead of ADSP. The differences between cycles initiated
with ADSC and ADSP are as follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
LW, UW is sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst accesses as shown below. The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion.
BURST SEQUENCE TABLE
(Interleaved Burst)
Case 1
A
1
A
0
First Address
0
0
1
1
1
Case 2
Case 3
Case 4
A
1
0
0
1
1
A
0
1
0
1
0
A
1
1
1
0
0
A
0
0
1
0
1
A
1
1
1
0
0
A
0
1
0
1
0
Fourth Address
0
1
0
LOGIC BLOCK DIAGRAM
K
ADSC
ADSP
ADV
CS
UW
LW
OE
I/O
0
~ I/O
17
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
64Kx18
MEMORY
ARRAY
ADDRESS
REGISTER
CONTROL
LOGIC
OUTPUT
BUFFER
DATA-IN
REGISTER
A
′
0
~A
′
1
A
0
~A
1
A
2
~A
15
A
0
~A
15
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相關(guān)代理商/技術(shù)參數(shù) |
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| KM718FV4021 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18 Synchronous Pipelined SRAM |
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| KM718FV4021H-6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18 Synchronous Pipelined SRAM |
| KM718FV4021H-7 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Kx36 & 256Kx18 Synchronous Pipelined SRAM |
| KM718N | 制造商:FRONTIER 制造商全稱:Frontier Electronics. 功能描述:10mm Adjustable Unshielded IFT Coils |
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