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參數(shù)資料
| 型號： | KM416V4004C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4M x 16bit CMOS Dynamic RAM with Extended Data Out(4M x 16位 CMOS動(dòng)態(tài)RAM(帶擴(kuò)展數(shù)據(jù)輸出)) |
| 中文描述： | 4米× 16位的擴(kuò)展數(shù)據(jù)輸出的CMOS動(dòng)態(tài)RAM（4米× 16位的CMOS動(dòng)態(tài)隨機(jī)存儲器（帶擴(kuò)展數(shù)據(jù)輸出）） |
| 文件頁數(shù)： | 9/36頁 |
| 文件大小： | 732K |
| 代理商： | KM416V4004C |
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KM416V4004C,KM416V4104C
CMOS DRAM
t
CWL
is specified from W falling edge to the earlier CAS rising edge.
t
CSR
is referenced to earlier CAS falling before RAS transition low.
t
CHR
is referenced to the later CAS rising high after RAS transition low.
t
DS
is specified for the earlier CAS falling edge and
t
DH
is specified by the later CAS falling edge in early write cycle.
If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
t
ASC
≥
6ns, Assume t
T
=2.0ns, if t
ASC
≤
6ns, then t
HPC
(min) and t
CAS
(min) must be increased by the value of "6ns-t
ASC
".
If
t
RASS
≥
100us, then RAS precharge time must use
t
RPS
instead of
t
RP
.
For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and
after self refresh in order to meet refresh specification.
t
CSR
t
CHR
RAS
LCAS
UCAS
t
DS
t
DH
LCAS
UCAS
DQ0 ~ DQ15
Din
22.
21.
20.
19.
18.
17.
16.
23.
24.
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| KM416V4100B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 16bit CMOS Dynamic RAM with Fast Page Mode |
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| KM416V4104B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 16bit CMOS Dynamic RAM with Extended Data Out |
| KM416V4104C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 16bit CMOS Dynamic RAM with Extended Data Out |
| KM416V4104CS-45 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 16bit CMOS Dynamic RAM with Extended Data Out |
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