THERMAL ADDENDUM (REV 3.0) Figure 22. Surface" />
參數(shù)資料
型號(hào)： KIT908E624DWBEVB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 30/39頁(yè)
文件大小： 0K
描述： KIT EVAL 908E624 TRPL W/MCU/LIN
標(biāo)準(zhǔn)包裝： 1
系列： HC08, SMARTMOS™
類型： MCU
適用于相關(guān)產(chǎn)品： MM908E624
所含物品： 板，線纜，CD
相關(guān)產(chǎn)品： MM908E624ACEWR2DKR-ND - IC SWITCH TRPL HI MCU/LIN 54SOIC
MM908E624ACEWR2CT-ND - IC SWITCH TRPL HI MCU/LIN 54SOIC
MM908E624ACDWB-ND - IC TRPL SWITCH MCU/LIN 54-SOIC
MM908E624ACDWBR2-ND - IC TRPL SWITCH MCU/LIN 54-SOIC
MM908E624AYEWR2-ND - IC TRPL SWITCH MCU/LIN 54-SOIC
MM908E624AYEW-ND - IC TRPL SWITCH MCU/LIN 54-SOIC
MM908E624ACEWR2TR-ND - IC SWITCH TRPL HI MCU/LIN 54SOIC
MM908E624ACEW-ND - IC SWITCH TRIPLE MCU/LIN 54-SOIC
Analog Integrated Circuit Device Data
36
Freescale Semiconductor
908E624
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
Figure 22. Surface Mount for SOIC Wide Body
Non-exposed Pad
Device on Thermal Test Board
RθJAmn is the thermal resistance between die junction and
ambient air.
This device is a dual die package. Index m indicates the
die that is heated. Index n refers to the number of the die
where the junction temperature is sensed.
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
PTA3/KBD3
PTA4/KBD4
VREFH
VDDA
EVDD
EVSS
VSSA
VREFL
PTE1/RXD
NC
RXD
WDCONF
+E
-E
OUT
VCC
AGND
VDD
NC
VSUP1
GND
LIN
VSUP2
FLSVPP
PTB7/AD7/TBCH1
PTB6/AD6/TBCH0
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTB5/AD5
PTB4/AD4
PTB3/AD3
IRQ
RST
PTB1/AD1
PTD0/TACH0
PTD1/TACH1
NC
PWMIN
RST_A
IRQ_A
NC
L1
L2
HS3
HS2
HS1
1
11
12
13
14
15
16
17
18
19
20
9
10
21
22
23
24
25
26
27
6
7
8
4
5
2
3
54
44
43
42
41
40
39
38
37
36
35
46
45
34
33
32
31
30
29
28
49
48
47
51
50
53
52
908E624 Pin Connections
54-Pin SOICW
0.65 mm Pitch
17.9 mm x 7.5 mm Body
A
Material:
Single layer printed circuit board
FR4, 1.6 mm thickness
Cu traces, 0.07 mm thickness
Outline:
80 mm x 100 mm board area,
including edge connector for thermal
testing
Area A:
Cu heat-spreading areas on board
surface
Ambient Conditions: Natural convection, still air
Table 17. Thermal Resistance Performance
Pin
Resistance
Area A
(mm2)
1 = Power Chip, 2 = Logic Chip (
°C/W)
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
RθJAmn
058
48
53
300
56
46
51
600
54
45
50
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