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參數(shù)資料
| 型號： | KIT908E624DWBEVB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 29/39頁 |
| 文件大小： | 0K |
| 描述： | KIT EVAL 908E624 TRPL W/MCU/LIN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | HC08, SMARTMOS™ |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | MM908E624 |
| 所含物品： | 板，線纜，CD |
| 相關(guān)產(chǎn)品： | MM908E624ACEWR2DKR-ND - IC SWITCH TRPL HI MCU/LIN 54SOIC MM908E624ACEWR2CT-ND - IC SWITCH TRPL HI MCU/LIN 54SOIC MM908E624ACDWB-ND - IC TRPL SWITCH MCU/LIN 54-SOIC MM908E624ACDWBR2-ND - IC TRPL SWITCH MCU/LIN 54-SOIC MM908E624AYEWR2-ND - IC TRPL SWITCH MCU/LIN 54-SOIC MM908E624AYEW-ND - IC TRPL SWITCH MCU/LIN 54-SOIC MM908E624ACEWR2TR-ND - IC SWITCH TRPL HI MCU/LIN 54SOIC MM908E624ACEW-ND - IC SWITCH TRIPLE MCU/LIN 54-SOIC |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
35
908E624
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
INTRODUCTION
This thermal addendum is provided as a supplement to the MM908E624
technical datasheet. The addendum provides thermal performance information
that may be critical in the design and development of system applications. All
electrical, application, and packaging information is provided in the datasheet.
Packaging and Thermal Considerations
The MM908E624 is a dual die package. There are two heat sources in the
package independently heating with P1 and P2. This results in two junction
temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn.
For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P1.
For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P2. This applies to
RθJ21 and RθJ22, respectively.
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a
package in an application-specific environment. Stated values were obtained by measurement and simulation according to the
standards listed below
Standards
54-Pin
SOICW
908E624
EW (Pb-FREE) SUFFIX
98ASA99294D
54-Pin SOICW
Note
For package dimensions, refer to
98ASA99294D.
TJ1
TJ2
=
RθJA11
RθJA21
RθJA12
RθJA22
.
P1
P2
Table 16. Thermal Performance Comparison
Thermal
Resistance
1 = Power Chip, 2 = Logic Chip [
°C/W]
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
RθJAmn
40
31
36
RθJBmn
25
16
21
RθJAmn
57
47
52
RθJCmn
21
12
16
Notes:
1.
Per JEDEC JESD51-2 at natural convection, still air
condition.
2.
2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3.
Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4.
Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5.
Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
54 Terminal SOIC
0.65 mm Pitch
17.9 mm x 7.5 mm Body
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