參數(shù)資料
型號(hào)： KB2514
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
中文描述： 視頻放大器合并OSD處理器的顯示器
文件頁數(shù)： 45/55頁
文件大小： 563K
代理商： KB2514
KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
44
Preliminary
- DOT0, 1 (Input)
Mode control signal that controls the number of dots per line in the frame control register. There are 4 modes:
320, 480, 640, and 800 dots/line.
According to your choice of mode, the OSD_PLL block's N-Divider is controlled by one of
÷
320,
÷
480,
÷
640, or
÷
800 Divider.
- HF0, 1, 2 (Input)
The horizontal Sync frequency information is received from the micro controller through the frame control
registers-1's bit C-A.
- CP0, 1 (Input)
Charge Pump's output sourcing (or sinking) current control pin.
This control data is received through frame control registers-1's bits E-D.
- VCO_OUT (Output)
VCO output that becomes a system clock. It is the OSD R, G, B output signal's dot frequency, and the standard
signal for OSD's various timings.
Also, it is input into the N-Divider and makes a PLL loop
- CP_OUT (Output)
Charge Pump circuit's output. input into external loop filter. It becomes one of 3 states according to the standard
signal input into the phase detector (HFLB) and the divider output (Div_Out).
- HFLB Div_Out is lead: Current sink
- HFLB Lag: Current source
- HFLB In-Phase: High impedence
fcl k
< 0. 4V
> 4. 2V
Ri se Ti m : < 4nS
Fal l Ti m : < 4nS
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