參數(shù)資料
型號： KB2514
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
中文描述： 視頻放大器合并OSD處理器的顯示器
文件頁數(shù)： 43/55頁
文件大?。?/td> 563K
代理商： KB2514
KB2514 VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
42
Preliminary
PLL CONTROL
Introduction
PLL (Phase Lock Loop) is feedback controlled circuit that maintains a constant phase difference between a
reference signal and an oscillator output signal.
Generally, PLL is composed as follow Figure.
- PFD (Phase Frequency Detector)
PFD compares the phase of the VCO output frequency, with the phase of a reference signal frequency output
pulse is generated in proportion to that phase difference.
- LF (Loop Filter)
LF smooths the output pulse of the phase detector and the resulting DC component is the VCO input.
- VCO (Voltage Controlled Oscillator)
VCO is controlled by loop filter output. The output of the VCO is fed back to the phase frequency detector
input for comparison which in turn controls the VCO oscillating frequency to minimize the phase difference.
- FD (Frequency Divider)
FD divides too much different frequency that is oscillated from the VCO to compare it with reference signal
frequency.
Figure 17. Block Diagram of General PLL
PFD
(Phase Frequency Detector)
LF
(Loop Filter)
VCO (Voltage
Controlled Oscillator)
FD
(Frequency Detector)
Reference Signal
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