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參數(shù)資料
| 型號(hào)： | KAD5612P-17Q72 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 8/29頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 170MSPS DUAL 72-QFN |
| 產(chǎn)品培訓(xùn)模塊： | High-Speed Analog-to-Digital Converters |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 170M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 405mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-QFN（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個(gè)差分，單極 |
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16
FN6803.2
September 9, 2009
An RF transformer will give the best noise and distortion
performance for wideband and/or high intermediate
frequency (IF) inputs. Two different transformer input
This dual transformer scheme is used to improve
common-mode rejection, which keeps the common-mode
level of the input matched to VCM. The value of the shunt
resistor should be determined based on the desired load
impedance. The differential input resistance of the
KAD5612P is 1000
Ω.
The SHA design uses a switched capacitor input stage (see
Figure 42), which creates current spikes when the sampling
capacitance is reconnected to the input voltage. This causes
a disturbance at the input which must settle before the next
sampling point. Lower source impedance will result in faster
settling and improved performance. Therefore a 1:1
transformer and low shunt resistance are recommended for
optimal performance.
A differential amplifier, as shown in Figure 29, can be used in
applications that require dc-coupling. In this configuration
the amplifier will typically dominate the achievable SNR and
distortion performance.
Clock Input
The clock input circuit is a differential pair (see Figure 43).
Driving these inputs with a high level (up to 1.8VP-P on each
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels.
The recommended drive circuit is shown in Figure 30. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may
impact SNR performance. The clock inputs are internally
self-biased to AVDD/2 to facilitate AC coupling.
A selectable 2x frequency divider is provided in series with
the clock input. The divider can be used in the 2x mode with
a sample clock equal to twice the desired sample rate. This
allows the use of the Phase Slip feature, which enables
synchronization of multiple ADCs.
The clock divider can also be controlled through the SPI
port, which overrides the CLKDIV pin setting. Details on this
are contained in “Serial Peripheral Interface” on page 19.
FIGURE 26. ANALOG INPUT RANGE
1.0
1.8
0.6
0.2
1.4
INP
INN
VCM
0.535V
0.725V
FIGURE 27. TRANSFORMER INPUT FOR GENERAL
PURPOSE APPLICATIONS
ADT1-1WT
0.1F
KAD5612P
VCM
ADT1-1WT
1000pF
FIGURE 28. TRANSMISSION-LINE TRANSFORMER INPUT
ADTL1-12
0.1F
KAD5612P
VCM
ADTL1-12
1000pF
TABLE 1. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
Float
1
AVDD
4
FIGURE 29. DIFFERENTIAL AMPLIFIER INPUT
KAD5612P
VCM
0.1F
0.22F
69.8O
49.9O
100O
69.8O
348O
CM
217O
25O
Ω
FIGURE 30. RECOMMENDED CLOCK DRIVE
TC4-1W
200pF
200O
200pF
CLKP
CLKN
1000pF
Ω
KAD5612P
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