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參數(shù)資料
| 型號(hào)： | KAD5612P-17Q72 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 170MSPS DUAL 72-QFN |
| 產(chǎn)品培訓(xùn)模塊： | High-Speed Analog-to-Digital Converters |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 170M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 405mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-QFN（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個(gè)差分，單極 |
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14
FN6803.2
September 9, 2009
Theory of Operation
Functional Description
The KAD5612P is based upon a 12-bit, 250MSPS A/D
converter core that utilizes a pipelined successive
approximation architecture (Figure 22). The input voltage is
captured by a Sample-Hold Amplifier (SHA) and converted
to a unit of charge. Proprietary charge-domain techniques
are used to successively compare the input to a series of
reference charges. Decisions made during the successive
approximation operations determine the digital code for each
input value. The converter pipeline requires six samples to
produce a result. Digital error correction is also applied,
resulting in a total latency of seven and one half clock cycles.
This is evident to the user as a latency between the start of a
conversion and the data being available on the digital
outputs.
matched transfer characteristics. At start-up, each core
performs a self-calibration to minimize gain and offset errors.
The reset pin (RESETN) is initially set high at power-up and
will remain in that state until the calibration is complete. The
clock frequency should remain fixed during this time, and no
SPI communications should be attempted. Recalibration can
be initiated via the SPI port at any time after the initial
self-calibration.
Power-On Calibration
The ADC performs a self-calibration at start-up. An internal
power-on-reset (POR) circuit detects the supply voltage
ramps and initiates the calibration when the analog and
digital supply voltages are above a threshold. The following
conditions must be adhered to for the power-on calibration to
execute successfully:
A frequency-stable conversion clock must be applied to
the CLKP/CLKN pins
DNC pins (especially pins 3, 4 and 18) must not be pulled
up or down
SDO (pin 66) must be high
RESETN (pin 25) must begin low
SPI communications must not be attempted
A user-initiated reset can subsequently be invoked in the
event that the above conditions cannot be met at power-up.
The SDO pin requires an external 4.7k
Ω pull-up to OVDD. If
the SDO pin is pulled low externally during power-up,
calibration will not be executed properly.
After the power supply has stabilized the internal POR
releases RESETN and an internal pull-up pulls it high, which
starts the calibration sequence. If a subsequent
user-initiated reset is required, the RESETN pin should be
connected to an open-drain driver with a drive strength of
less than 0.5mA.
FIGURE 22. ADC CORE BLOCK DIAGRAM
DIGITAL
ERROR
CORRECTION
SHA
1.25V
INP
INN
CLOCK
GENERATION
2.5-BIT
FLASH
6-STAGE
1.5-BIT/STAGE
3-STAGE
1-BIT/STAGE
3-BIT
FLASH
LVDS/LVCMOS
OUTPUTS
+
–
KAD5612P
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