參數(shù)資料
型號(hào)： KAD5612P-17Q72
廠商： Intersil
文件頁(yè)數(shù)： 10/29頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 170MSPS DUAL 72-QFN
產(chǎn)品培訓(xùn)模塊： High-Speed Analog-to-Digital Converters
標(biāo)準(zhǔn)包裝： 1
系列： FemtoCharge™
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 405mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 72-QFN（10x10）
包裝： 托盤
輸入數(shù)目和類型： 2 個(gè)差分，單極
18
FN6803.2
September 9, 2009
Wake-up from Sleep Mode Sequence (CSB high)
Pull CSB Low
Wait 150us
Write ‘001x’ to Register 25
Wait 1ms until ADC fully powered on
In an application where CSB was kept low in sleep mode, the
150s CSB setup time is not required as the SPI registers are
powered on when CSB is low, the chip power dissipation
increases by ~ 15mW in this case. The 1ms wake-up time
after the write of a ‘001x’ to register 25 still applies. It is
generally recommended to keep CSB high in sleep mode to
avoid any unintentional SPI activity on the ADC.
All digital outputs (Data, CLKOUT and OR) are placed in a
high impedance state during Nap or Sleep. The input clock
should remain running and at a fixed frequency during Nap
or Sleep, and CSB should be high. Recovery time from Nap
mode will increase if the clock is stopped, since the internal
DLL can take up to 52s to regain lock at 250MSPS.
By default after the device is powered on, the operational
state is controlled by the NAPSLP pin as shown in Table 3.
The power-down mode can also be controlled through the
SPI port, which overrides the NAPSLP pin setting. Details on
page 19. This is an indexed function when controlled from
the SPI, but a global function when driven from the pin.
Data Format
Output data can be presented in three formats: two’s
complement, Gray code and offset binary. The data format is
selected via the OUTFMT pin as shown in Table 4.
The data format can also be controlled through the SPI port,
which overrides the OUTFMT pin setting. Details on this are
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF
(all ones). Two’s complement coding simply complements
the MSB of the offset binary representation.
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 32 shows
this operation.
Converting back to offset binary from Gray code must be
done recursively, using the result of each bit for the next
lower bit as shown in Figure 33.
Mapping of the input voltage to the various data formats is
shown in Table 5.
TABLE 3. NAPSLP PIN SETTINGS
NAPSLP PIN
MODE
AVSS
Normal
Float
Sleep
AVDD
Nap
TABLE 4. OUTFMT PIN SETTINGS
OUTFMT PIN
MODE
AVSS
Offset Binary
Float
Two’s Complement
AVDD
Gray Code
TABLE 5. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT
VOLTAGE
OFFSET
BINARY
TWO’S
COMPLEMENT
GRAY CODE
–Full Scale 000 00 000 00 00 100 00 000 00 00 000 00 000 00 00
–Full Scale
+1LSB
000 00 000 00 01 100 00 000 00 01 000 00 000 00 01
Mid–Scale 100 00 000 00 00 000 00 000 00 00 110 00 000 00 00
+Full Scale
– 1LSB
111 11 111 11 10 011 11 111 11 10 100 00 000 00 01
+Full Scale
111 11 111 11 11
011 11 111 111 1 100 00 000 00 00
FIGURE 32. BINARY TO GRAY CODE CONVERSION
10
11
9
0
1
BINARY
10
11
9
0
GRAY CODE
1
FIGURE 33. GRAY CODE TO BINARY CONVERSION
10
11
9
0
1
BINARY
10
11
9
0
GRAY CODE
1
KAD5612P
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