參數(shù)資料
型號: K9K1208U0M
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 64M x 8 Bit NAND Flash Memory
中文描述: 6400 × 8位NAND閃存
文件頁數(shù): 24/26頁
文件大小: 354K
代理商: K9K1208U0M
K9K1208U0M-YCB0, K9K1208U0M-YIB0
FLASH MEMORY
24
Figure 9. Read ID Operation
CE
CLE
I/O
0
~
7
ALE
RE
WE
90h
00h
ECh
76h
Address. 1cycle
Maker code
Device code
t
CR
t
AR1
t
READID
Figure 10. RESET Operation
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 10 below.
After Power-up
After Reset
Operation Mode
Read 1
Waiting for next command
FFh
I/O
0
~
7
R/B
Table3. Device Status
t
RST
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECH), and the device code (76H) respectively. The command regis-
ter remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
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