參數(shù)資料
型號(hào): K9K1208U0M
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 64M x 8 Bit NAND Flash Memory
中文描述: 6400 × 8位NAND閃存
文件頁(yè)數(shù): 13/26頁(yè)
文件大?。?/td> 354K
代理商: K9K1208U0M
K9K1208U0M-YCB0, K9K1208U0M-YIB0
FLASH MEMORY
13
System Interface Using CE don’t-care.
CE
WE
t
WP
t
CH
Timing requirements : If CE is is exerted high during data-loading,
tCS must be minimum 10ns and tWC must be increased accordingly.
t
CS
(Min. 10ns)
Start Add.(4Cycle)
80h
Data Input
CE
CLE
ALE
WE
I/O
0
~
7
Data Input
CE don’t-care
10h
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
Start Add.(4Cycle)
00h
CE
CLE
ALE
WE
I/O
0
~
7
Data Output(sequential)
CE don’t-care
R/B
t
R
RE
t
CEA
out
t
REA
(Max. 45ns)
CE
RE
I/O
0
~
7
Timing requirements : If CE is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 45ns.
Figure 3. Program Operation with CE don’t-care.
Figure 4. Read Operation with CE don’t-care.
Must be held
low during tR.
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