參數(shù)資料
型號(hào)： K9F8008W0M-TCB0
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
元件分類(lèi)： 圓形連接器
英文描述： Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVPS00; No. of Contacts:37; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight
中文描述： 100萬(wàn)× 8位NAND快閃記憶體
文件頁(yè)數(shù)： 4/25頁(yè)
文件大?。?/td> 445K
代理商： K9F8008W0M-TCB0
K9F8008W0M-TCB0, K9F8008W0M-TIB0
FLASH MEMORY
4
PRODUCT INTRODUCTION
The K9F8008W0M is an 8.6Mbit(8,650,752 bit) memory organized as 4096 rows by 264 columns. Spare eight columns are located
from column address of 256 to 263. A 264-byte data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that
are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16 pages
formed by one NAND structures, totaling 2,112 NAND structures of 16 cells. The array organization is shown in Figure 2. The pro-
gram and read operations are executed on a page basis, while the erase operation is executed on block basis. The memory array
consists of 256 separately or grouped erasable 4K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9F8008W0M.
The K9F8008W0M has addresses multiplexed into 8 I/O
′
s. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O
′
s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles : a cycle for erase-setup and another for erase-execution after block
address loading. The 2M byte physical space requires 21 addresses, thereby requiring three cycles for byte-level addressing : col-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same three address
cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the K9F8008W0M.
Table 1. COMMAND SETS
Function
1st. Cycle
2nd. Cycle
Acceptable Command during Busy
Sequential Data Input
80h
-
Read 1
00h
-
Read 2
50h
-
Read ID
90h
-
Reset
FFh
-
O
Page Program
10h
-
Block Erase
60h
D0h
Read Status
70h
-
O
相關(guān)PDF資料
PDF描述
K9F8008W0M-TIB0 Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVPS00; Number of Contacts:37; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Body Style:Straight
K9K1208U0A-YCB0 TV 16C 16#16 SKT RECP
K9K1208U0A-YIB0 64M x 8 Bit NAND Flash Memory
K9K1208U0M 64M x 8 Bit NAND Flash Memory
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參數(shù)描述
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K9F8G08U0M-PCK0000 制造商:Samsung 功能描述:K9F8G08U0M-PCK0000NAND FLASH - Trays
K9G4G08B0A 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:Preliminary FLASH MEMORY
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