參數(shù)資料
型號(hào)： K8S1215EZC-SC1C0
元件分類： PROM
英文描述： 32M X 16 FLASH 1.8V PROM, 100 ns, PBGA64
封裝： 9 X 11 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, FBGA-64
文件頁數(shù)： 17/83頁
文件大小： 1511K
代理商： K8S1215EZC-SC1C0
Figure 3. DPD Timings
- 24 -
K8S1215E(T/B/Z)C
datasheet NOR FLASH MEMORY
Rev. 1.1
11.0 Deep Power Down
In order to reduce the power consumption of the device, it shall a deep power down mode implemented on a separate pin. The deep power down mode is
active when the deep power down signal is activated, high state. In deep power down the device shall turn off all circuitry in order to reach a power con-
sumption of 2uA(typ). The device shall exit the deep power down mode within 75us after that the deep power down signal has been de-activated, set to
low. In deep power down the state of the device chip select shall have no impact on the device power consumption. All programming capabilities of the
device are inhibited.
At the power up, the device shall accept any order of activation of the reset and deep power down signal. The device shall respond within the specified
time for the signal that was deactivated/activated latest. The deep power down mode is activated when DPD pin high state only. If DPD is asserted during
a program or erase operation, the device requires a time of tDP(During Internal Routines) before the device is ready to enter DPD mode.
Note that user never float the DPD that is, DPD is always connected with VIH, VIL.
Deep Power Down (DPD)
NOTE : Not 100% tested.
SWITCHING WAVEFORMS
DPD Timings NOT during Internal Routines
DPD Timings during Internal Routines
Parameter
Symbol
All Speed Options
Unit
Min
Typ
Max
DPD Pin High (NOT During Internal Routines)
to DPD Mode*
tDP
100
-
ns
DPD Pin High (During Internal Routines)
to DPD Mode*
tDP
20
-
μs
DPD Low Time Before Read*
twkup
75
-
μs
twkup
CE, OE
DPD
tDP
twkup
CE, OE
≈
tDP
DPD
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