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參數(shù)資料
| 型號： | K7A803600M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx36 & 512Kx18 Synchronous SRAM |
| 中文描述： | 256Kx36 |
| 文件頁數(shù)： | 17/21頁 |
| 文件大?。?/td> | 542K |
| 代理商： | K7A803600M |
K7A801800M
256Kx36 & 512Kx18 Synchronous SRAM
- 17 -
Rev 6.0
March 2000
K7A803600M
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 256Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.
Data
Address
CLK
ADS
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV
ADSP
256Kx36
SPB
SRAM
(Bank 0)
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV
ADSP
256Kx36
SPB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A
[0:18]
A
[18]
A
[0:17]
A
[18]
A
[0:17]
I/O
[0:71]
Microprocessor
INTERLEAVE READ TIMING
(Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
Clock
ADSP
ADDRESS
[0:n]
Data Out
(Bank 0)
Bank 0 is selected by
CS
2
, and Bank 1 deselected by
CS
2
Q1-1
Q1-2
Q1-4
Q1-3
OE
Data Out
(Bank 1)
t
SS
t
SH
A1
A2
WRITE
CS
1
A
n+1
ADV
Q2-2
Q2-4
Q2-3
t
AS
t
AH
t
WS
t
WH
t
ADVS
t
ADVH
t
OE
t
LZOE
t
HZC
Bank 0 is deselected by
CS
2
, and Bank 1 selected by
CS
2
t
CSS
t
CSH
CD
t
LZC
Q2-1
Don
′
t Care
Undefined
*Notes :
n = 14 32K depth , 15 64K depth
16 128K depth , 17 256K depth
18 512K depth
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| K7A803600M-QC14000 | 制造商:Samsung SDI 功能描述: |
| K7A803601M | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 Synchronous SRAM |
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| K7A803609B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM |
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