- 您現(xiàn)在的位置：買賣IC網 > PDF目錄374284 > K4T51043QC-ZCLE6 (SAMSUNG SEMICONDUCTOR CO. LTD.) 512Mb C-die DDR2 SDRAM PDF資料下載
參數(shù)資料
| 型號： | K4T51043QC-ZCLE6 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Mb C-die DDR2 SDRAM |
| 中文描述： | 葷的512Mb芯片DDR2內存 |
| 文件頁數(shù)： | 28/29頁 |
| 文件大?。?/td> | 629K |
| 代理商： | K4T51043QC-ZCLE6 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當前第28頁第29頁
Page 28 of 29
Rev. 1.4 Aug. 2005
DDR2 SDRAM
512Mb C-die DDR2 SDRAM
31. Input waveform timing is referenced from the input signal crossing at the V
IH(ac)
level for a rising signal and V
IL(ac)
for a falling signal applied to the
device under test.
32. Input waveform timing is referenced from the input signal crossing at the V
IL(dc)
level for a rising signal and V
IH(dc)
for a falling signal applied to the
device under test.
33. tWTR is at lease two clocks (2 * tCK) independent of operation frequency.
34. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the sin-
gle-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-
ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic
between Vil(dc)max and Vih(dc)min.
35. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the sin-
gle-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the single-
ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic
between Vil(dc)max and Vih(dc)min.
36. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire
time it takes to achieve the 3 clocks of registeration. Thus, after any CKE transition, CKE may not change from its valid level during the time period of tIS
+ 2*tCK + tIH.
tIS
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
V
REF(dc)
V
IL(dc)
max
V
IL(ac)
max
V
SS
CK
CK
tIH
tIS
tIH
相關PDF資料 |
PDF描述 |
|---|---|
| K4T51043QC-ZCD5 | 512Mb C-die DDR2 SDRAM |
| K4 | KS SERIES KEY SWITCHES |
| K5-C | Adjustable Type Coils |
| K5-N | Adjustable Type Coils |
| K5-N1 | Adjustable Type Coils |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| K4T51043QC-ZLCC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mb C-die DDR2 SDRAM |
| K4T51043QC-ZLD5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mb C-die DDR2 SDRAM |
| K4T51043QC-ZLE6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mb C-die DDR2 SDRAM |
| K4T51043QC-ZLE7 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mb C-die DDR2 SDRAM |
| K4T51043QE | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mb E-die DDR2 SDRAM Specification |
發(fā)布緊急采購，3分鐘左右您將得到回復。