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參數(shù)資料
| 型號： | K4N56163QF-GC25 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Mbit gDDR2 SDRAM |
| 中文描述： | 片256Mbit GDDR2 SDRAM的 |
| 文件頁數(shù)： | 10/73頁 |
| 文件大?。?/td> | 1262K |
| 代理商： | K4N56163QF-GC25 |
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- 10 -
Rev 1.6 (Apr. 2005)
256M gDDR2 SDRAM
K4N56163QF-GC
OCD default characteristics
Notes:
1. Absolute Specifications (0°C
≤
T
CASE
≤
+95°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)
2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV;
less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-
280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than
23.4 ohms for values of VOUT between 0V and 280mV.
3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and
voltage.
4. Slew rate measured from V
IL
(AC) to V
IH
(AC).
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to
AC. This is guaranteed by design and characterization.
6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the
DRAM uncertainty.
(VOUT-VDDQ)/Ioh must be
Output slew rate load :
7. DRAM output slew rate specification applies to 533Mb/sec/pin, 667Mb/sec/pin, 800Mb/sec/pin, 900Mbps/sec/pin and
1000Mbps/sec/pin speed bins.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS
specification.
Description
Output impedance
Output impedance step size for
OCD calibration
Pull-up and pull-down mismatch
Output slew rate
Parameter
Min
Nom
Max
Unit
Notes
1,2
12.6
18
23.4
ohms
0
1.5
ohms
6
0
4
5
ohms
V/ns
1,2,3
1,4,5,6,7,8
Sout
1.5
25 ohms
V
TT
Output
(V
OUT)
Reference
Point
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