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參數(shù)資料
| 型號： | K4J55323QF-GC15 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Mbit GDDR3 SDRAM |
| 中文描述： | 片256Mbit GDDR3 SDRAM的 |
| 文件頁數(shù)： | 38/49頁 |
| 文件大?。?/td> | 1027K |
| 代理商： | K4J55323QF-GC15 |
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256M GDDR3 SDRAM
K4J55323QF-GC
Rev 1.8 (Apr. 2005)
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a
particular bank or the open row in all banks. The bank(s) will be available
for a subsequent row access some specified time (t
RP
) after the PRE-
CHARGE command is issued. Input A8 determines whether one or all
banks are to be precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. When all banks are to
be precharged, inputs BA0, BA1 are treated as "Don’t Care." Once a
bank has been precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to the bank.
POWER-DOWN (CKE NOT ACTIVE)
Unlike SDRAMs,GDDR3(x32) SDRAM requires CKE to be active at all
times an access is in progress; from the issuing of a READ or WRITE
command until completion of the burst. For READs, a burst completion is
defined when the Read Postamble is satisfied; For WRITEs, a burst
completion is defined BL/2 cycles after the Write Postamble is satisfied.
Power-down is entered when CKE is registered LOW. If power-down
occurs when there is a row active in any bank, this mode is referred to as
active power-down. Entering power-down deactivates the input and out-
put buffers, excluding CK,/CK and CKE. For maximum power savings,
the user has the option of disabling the DLL prior to entering power-
down. However, power-down duration is limited by the refresh require-
ments of the device, so in most applications,the self-refresh mode is pre-
ferred over the DLL-disabled power-down mode.
When in power-down, CKE LOW and a stable clock signal must be
maintained at the inputs of the GDDR3 SDRAM, while all other input sig-
nals are "Don’t Care."
The power-down state is synchronously exited when CKE is registered
HIGH (in conjunction with a NOP or DESELECT command). A valid exe-
cutable command may be applied six clock cycle later.
ALL BANKS
ONE BANK
BA
/CS
/RAS
/CAS
/WE
A0-A7, A9-A11
BA0,1
BA=Bank Address
(if A8 is LOW; otherwise "Don’t Care")
/CK
CK
CKE
HIGH
A8
DON’T CARE
PRECHARGE Command
NOP
NOP
NOP
VALID
T0
T1
Ta0
Ta1
Ta2
/CK
CK
COMMAND
VALID
Ta7
T2
CKE
t
IS
t
PDEX
t
IS
No PEAD/WRITE
access in progress
Enter power - down mode
Exit power - down mode
Power-Down
NOP
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| K4J55323QF-GC16 | 256Mbit GDDR3 SDRAM |
| K4J55323QF-GC20 | 256Mbit GDDR3 SDRAM |
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| K4M51163LE-F | 8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4J55323QF-GC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR3 SDRAM |
| K4J55323QF-GC20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR3 SDRAM |
| K4J55323QG | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR3 SDRAM |
| K4J55323QG-BC12 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR3 SDRAM |
| K4J55323QG-BC14 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR3 SDRAM |
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