參數(shù)資料
型號(hào)： K4J55323QF-GC15
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 256Mbit GDDR3 SDRAM
中文描述： 片256Mbit GDDR3 SDRAM的
文件頁(yè)數(shù)： 13/49頁(yè)
文件大?。?/td> 1027K
代理商： K4J55323QF-GC15
- 13 -
256M GDDR3 SDRAM
K4J55323QF-GC
Rev 1.8 (Apr. 2005)
WRITE LATENCY
The Write latency (WL) is the delay, in clock cycles, between the registration of a WRITE command and the availability of the first bit of
input data. The latency can be set from 1 to 6 clocks depending in the operating frequency and desired current draw. When the write
latencies are set to 1 or 2 or 3 clocks, the input receivers never turn off when the WRITE command is registered. If a WRITE command
is registered at clock edge
n
, and the latency is
m
clocks, the data will be available nominally coincident with clock edge
n
+
m
. Reserved
states should not be used as unknown operation or incompatibility with future versions may result.
* Maximum frequency of GDDR3 can be limited in WL4, 5 and 6
NOP
NOP
NOP
WRITE
T0
T1
T3
T3n
/CK
CK
COMMAND
T2
DQ
WL = 3
NOP
NOP
NOP
WRITE
T0
T2
T4
T4n
/CK
CK
COMMAND
T3
DQ
WL = 4
Burst Length = 4 in the cases shown
DON’T CARE
TRANSITIONING DATA
WDQS
WDQS
～～
～～
～～
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