參數(shù)資料
型號: K4J52324KI-HC1A0
元件分類: DRAM
英文描述: 512M X 1 DDR DRAM, 0.2 ns, PBGA136
封裝: HALOGEN FREE AND ROHS COMPLIANT, FBGA-136
文件頁數(shù): 54/61頁
文件大?。?/td> 1364K
代理商: K4J52324KI-HC1A0
- 58 -
K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
NOTE : 1. The alternative solution for 8bank activation without tFAW restriction is to set tRRD=12ns regardless of frequency. In this case, the minimum number of clock cycles
is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer unconditionally.
Parameter
Symbol
-HC12(800MHz)
-HC14(700MHz)
Unit
NOTE
Min
Max
Min
Max
Row active time
tRAS
25
100K
22
100K
tCK
Row cycle time
tRC
35
-
31
-
tCK
Refresh row cycle time
tRFC
45
-
39
-
tCK
RAS to CAS delay for Read
tRCDR
12
-
10
-
tCK
RAS to CAS delay for Write
tRCDW
8
-
6
-
tCK
Row precharge time
tRP
10
-
9
-
tCK
Row active to Row active
tRRD
8
-
8
-
tCK
Four activate window
tFAW
40
-
40
-
tCK
1
Last data in to Row precharge (PRE or Auto-PRE)
tWR
11
-
10
-
tCK
Last data in to Read command
tCDLR
6
-
5
-
tCK
CAS to CAS command delay
tCCD
BL/2
-
BL/2
-
tCK
Mode register set cycle time
tMRD
7
-
6
-
tCK
Auto precharge write recovery time + Precharge
tDAL
21
-
19
-
tCK
Exit self refresh to Read command
tXSR
20000
-
20000
-
tCK
Exit self refresh to Non-Read command
tXSNR
100
-
100
-
tCK
Power-down exit time
tPDEX
7tCK+tIS
-
6tCK
+tIS
-tCK
Refresh interval time
tREF
-
3.9
-
3.9
us
CKE minimum pulse width
(High and Low pulse width)
tCKE
5-5-
tCK
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