參數(shù)資料
型號: K4J52324KI-HC1A0
元件分類: DRAM
英文描述: 512M X 1 DDR DRAM, 0.2 ns, PBGA136
封裝: HALOGEN FREE AND ROHS COMPLIANT, FBGA-136
文件頁數(shù): 4/61頁
文件大小: 1364K
代理商: K4J52324KI-HC1A0
- 12 -
K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
CAS LATENCY (READ LATENCY)
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency
can be set to 7~15 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident
with clock edge n+m. Below table indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be
used as unknown operation or incompatibility with future versions may result.
[ Table 2 ] CAS Latency
SPEED
Allowable CAS Latency
CL=15
CL=14
CL=12
CL=11
CL=10
1300MHz
O
-
1200MHz
O
-
1000MHz
O
-
800MHz
O
-
700MHz
O
NOP
READ
T0
T5
T7
T7n
CK
COMMAND
T6
RDQS
DQ
CL = 7
NOP
READ
T0
T6
T8
T8n
CK
COMMAND
T7
RDQS
DQ
CL = 8
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ
DON’T CARE
TRANSITIONING DATA
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