參數(shù)資料
型號(hào)： K4H560438D-GCB3
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： DDR 256Mb
中文描述： 的DDR 256Mb的
文件頁(yè)數(shù)： 11/26頁(yè)
文件大?。?/td> 291K
代理商： K4H560438D-GCB3
- 11 -
K4H560438D
DDR SDRAM
Rev. 2.2 Mar. ’03
AC Timming Parameters & Specifications
Parameter
Symbol
B3
(DDR333)
Min
A2
(DDR266A)
Min
B0
(DDR266B)
Min
Unit
Note
Max
Max
Max
Row cycle time
tRC
60
65
65
ns
Refresh row cycle time
tRFC
72
75
75
ns
Row active time
tRAS
42
70K
45
120K
45
120K
ns
RAS to CAS delay
tRCD
18
20
20
ns
Row precharge time
tRP
18
20
20
ns
Row active to Row active delay
tRRD
12
15
15
ns
Write recovery time
tWR
15
15
15
ns
Last data in to Read command
tWTR
1
1
1
tCK
Col. address to Col. address delay
tCCD
1
1
1
tCK
Clock cycle time
CL=2.0
tCK
7.5
12
7.5
12
10
12
ns
5
CL=2.5
6
12
7.5
12
7.5
12
ns
5
Clock high level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock low level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS-out access time from CK/CK
tDQSCK
-0.6
+0.6
-0.75
+0.75
-0.75
+0.75
ns
Output data access time from CK/CK
tAC
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Data strobe edge to ouput data edge
tDQSQ
-
0.4
-
0.5
-
0.5
ns
5
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS-in setup time
tWPRES
0
0
0
ns
2
DQS-in hold time
tWPRE
0.25
0.25
0.25
tCK
DQS falling edge to CK rising-setup time
tDSS
0.2
0.2
0.2
tCK
DQS falling edge from CK rising-hold time
tDSH
0.2
0.2
0.2
tCK
DQS-in high level width
tDQSH
0.35
0.35
0.35
tCK
DQS-in low level width
tDQSL
0.35
0.35
0.35
tCK
DQS-in cycle time
tDSC
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Address and Control Input setup time(fast)
tIS
0.75
0.9
0.9
ns
6
Address and Control Input hold time(fast)
tIH
0.75
0.9
0.9
ns
6
Address and Control Input setup time(slow)
tIS
0.8
1.0
1.0
ns
6
Address and Control Input hold time(slow)
tIH
0.8
1.0
1.0
ns
6
Data-out high impedence time from CK/CK
tHZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Data-out low impedence time from CK/CK
tLZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Input Slew Rate(for input only pins)
tSL(I)
0.5
0.5
0.5
V/ns
6
Input Slew Rate(for I/O pins)
tSL(IO)
0.5
0.5
0.5
V/ns
7
Output Slew Rate(x4,x8)
tSL(O)
1.0
4.5
1.0
4.5
1.0
4.5
V/ns
10
Output Slew Rate Matching Ratio(rise to fall)
tSLMR
0.67
1.5
0.67
1.5
0.67
1.5
相關(guān)PDF資料
PDF描述
K4H560438D-GLA2 DDR 256Mb
K4H560438E-ZLB0 Connector Kit; Contents Of Kit:C14610F0240001 24 position bulkhead housing double latch, C14610B0241021 24 position female insert wire protect, Without spring cover; For Use With:C146 Heavy Duty Industrial Connectors RoHS Compliant: Yes
K4H560438E-ZLB3 Connector Kit; Contents Of Kit:C14610G0245001 24 position hood PG 21 double latch low profile side entry, C14610A0241021 24 position male insert wire protect, VN162100014 PG 21 gland bushing, For 0.433" - 0.866" diameter cable RoHS Compliant: Yes
K4H560438E-ZLA2 Rectangular Industrial Connector Housing; Series:C-146; No. of Contacts:6; Gender:Female; Body Material:Aluminum Alloy; Connecting Termination:Screw; Features:Spring Cover; For Use With:C146 Rectangular Circular Connectors RoHS Compliant: Yes
K4H560438E-ZCB0 CSM, CER 103PF 1000V 10% 1210
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4H560438D-GLA2 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR 256Mb
K4H560438D-GLB0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR 256Mb
K4H560438D-GLB3 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR 256Mb
K4H560438D-NC 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb sTSOPII
K4H560438D-NC/LA0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb sTSOPII
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