參數(shù)資料
型號: K4H513238M-TLA2
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Quad Wide Bandwidth High Output Drive Single Supply Op Amp 14-SOIC -40 to 125
中文描述: 128MB DDR SDRAM的
文件頁數(shù): 52/53頁
文件大?。?/td> 669K
代理商: K4H513238M-TLA2
- 52 -
REV. 1.0 November. 2. 2000
128Mb DDR SDRAM
QFC timing on Write operation
QFC on writes is enabled as soon as possible after the clock edge of write command and disabled as soon
as possible after the last DQS-in low going edge.
2
0
1
5
3
4
6
7
Hi-Z
DQS@tDQSSmax
QFC
t
QCSW
*1
t
QCHW min.
Dout 0Dout 1
BL = 2
Write
DQ’S@tDQSSmax
Command
CK
CK
DQS@tDQSSmin
DQ’S@tDQSSmin
2
0
1
5
3
4
6
7
Hi-Z
QFC
t
QCSW
*1
t
QCHW min.
Dout 0 Dout 1
BL = 2
Write
Command
CK
CK
Figure 27. : QFC timing on write operation with tDQSSmax
Figure 28. : QFC timing on write operation with tDQSSmin
*2
t
QCHW max.
*2
t
QCHW max.
1. The value of tQCSW min. is 1.25ns from the last low going data strobe edge to QFC tri-state.
2. The value of tQCSW max. is 0.5tcK from the first high going clock edge after the last low going data strobe
edge to QFC tri-state.
相關(guān)PDF資料
PDF描述
K4H513238M-TLB0 Quad Wide Bandwidth High Output Drive Single Supply Op Amp 14-PDIP -40 to 125
K4H563238A-TCA2 10-Bit, 164 kSPS ADC Parallel Out, Direct I/F to DSP/uProcessor, 10 Ch. 24-SOIC -40 to 85
K4H563238A-TCB0 10-Bit, 164 kSPS ADC Parallel Out, Direct I/F to DSP/uProcessor, 10 Ch. 24-SOIC -40 to 85
K4H563238A-TLA0 10-Bit, 164 kSPS ADC Parallel Out, Direct I/F to DSP/uProcessor, 10 Ch. 28-PLCC -40 to 85
K4H563238A-TLA2 128Mb DDR SDRAM
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