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參數(shù)資料
| 型號： | K4D553238F-JC40 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Mbit GDDR SDRAM |
| 中文描述： | 片256Mbit GDDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 297K |
| 代理商： | K4D553238F-JC40 |
256M GDDR SDRAM
K4D553238F-JC
2M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
- 3 -
Rev 1.0 (Mar. 2004)
The K4D553238F is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by
32 bits, fabricated with SAMSUNG
’
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 2.8GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
2.5V + 5% power supply for device operation
2.5V + 5% power supply for I/O interface
SSTL_2 compatible inputs/outputs
4 banks operation
MRS cycle with address key programs
-. Read latency 3, 4 (clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
All inputs except data & DM are sampled at the positive
going edge of the system clock
Differential clock input
No Wrtie-Interrupted by Read Function
GENERAL DESCRIPTION
FEATURES
4 DQS’s ( 1DQS / Byte )
Data I/O transactions on both edges of Data strobe
DLL aligns DQ and DQS transitions with Clock transition
Edge aligned data & data strobe output
Center aligned data & data strobe input
DM for write masking only
Auto & Self refresh
32ms refresh period (4K cycle)
144-Ball FBGA
Maximum clock frequency up to 350MHz
Maximum data rate up to 700Mbps/pin
FOR 2M x 32Bit x 4 Bank GDDR SDRAM
ORDERING INFORMATION
1. K4D553238F-EC is the Lead Free package part number
2. For the K4D553238F-JC2A, VDD & VDDQ =2.8V + 0.1V
Part NO.
Max Freq.
Max Data Rate
Interface
Package
K4D553238F-JC2A
350MHz
700Mbps/pin
SSTL_2
144-Ball FBGA
K4D553238F-JC33
300MHz
600Mbps/pin
K4D553238F-JC36
275MHz
550Mbps/pin
K4D553238F-JC40
250MHz
500Mbps/pin
K4D553238F-JC50
200MHz
400Mbps/pin
相關(guān)PDF資料 |
PDF描述 |
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| K4D553238F-JC50 | 256Mbit GDDR SDRAM |
| K4E151611 | 1M x 16Bit CMOS Dynamic RAM with Extended Data Out |
| K4E151611D | 1M x 16Bit CMOS Dynamic RAM with Extended Data Out |
| K4E151612D | 1M x 16Bit CMOS Dynamic RAM with Extended Data Out |
| K4E171611D | 1M x 16Bit CMOS Dynamic RAM with Extended Data Out |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4D553238F-JC50 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR SDRAM |
| K4D55323QF-GC33 | 制造商:Samsung Semiconductor 功能描述: |
| K4D623237A-QC60 | 制造商:Samsung Semiconductor 功能描述: 制造商:Samsung Semiconductor 功能描述:2M X 32 DDR DRAM, 5.5 ns, PQFP100 |
| K4D623238B-GC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mbit DDR SDRAM |
| K4D623238B-GC/L33 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mbit DDR SDRAM |
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