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參數(shù)資料
| 型號： | K4D553235F-GC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256M GDDR SDRAM |
| 中文描述： | 256M GDDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 386K |
| 代理商： | K4D553235F-GC |
256M GDDR SDRAM
K4D553235F-GC
- 9 -
Rev 1.6 (May 2005)
The extended mode register stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore the extened mode register
must be written after power up for enabling or disabling DLL. The extended mode register is written by assert-
ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11
and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1
and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are
required to complete the write operation in the extended mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in
the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address
pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific
codes.
A
0
DLL Enable
0
Enable
1
Disable
BA
0
A
n
~ A
0
0
MRS
1
EMRS
Figure 7. Extended Mode Register set
EXTENDED MODE REGISTER SET(EMRS)
Address Bus
Extended
Mode Register
*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.
A
6
0
0
1
1
A
1
0
1
0
1
Output Driver Impedence Control
Full
100%
Weak
60%
N/A
Do not use
Matched
30%
RFU
1
RFU
D.I.C
RFU
D.I.C
DLL
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
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