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參數(shù)資料
| 型號： | K4D263238M-QC45 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DIODE ZENER DUAL COMMON-CATHODE 300mW 39Vz 5mA-Izt 0.0513 0.1uA-Ir 29 SOT-23 3K/REEL |
| 中文描述： | 100萬x 32Bit的× 4銀行雙數(shù)據(jù)速率同步RAM的雙向數(shù)據(jù)選通和DLL |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 281K |
| 代理商： | K4D263238M-QC45 |
128M DDR SDRAM
K4D263238M
- 9 -
Rev. 1.3 (Aug. 2001)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register must be
written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and
WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of
address pins A
0
~ A
11
and BA
0
, BA
1
in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.
Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields depending on functionality. The burst length uses A
0
~ A
2
,
addressing mode uses A
3
, CAS latency(read latency from column address) uses A
4
~ A
6
. A
7
is used for test mode. A
8
is
used for DLL reset. A
7,
A
8
, BA
0
and BA
1
must be set to low for normal MRS operation. Refer to the table for specific codes
for various burst length, addressing modes and CAS latencies.
MODE REGISTER SET(MRS)
Address Bus
Mode
Register
CAS Latency
A
6
0
0
0
0
1
1
1
1
A
5
0
0
1
1
0
0
1
1
A
4
0
1
0
1
0
1
0
1
Latency
Reserved
Reserved
Reserved
3
4
Reserved
Reserved
Reserved
Burst Length
A
2
A
1
A
0
Burst Type
Sequential
Reserve
2
4
8
Reserve
Reserve
Reserve
Full page
Interleave
Reserve
2
4
8
Reserve
Reserve
Reserve
Reserve
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Burst Type
A
3
0
1
Type
Sequential
Interleave
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
MRS Cycle
Command
*1: MRS can be issued only at all banks precharge state.
*2: Minimum
t
RP
is required to issue MRS command.
CK, CK
Precharge
All Banks
NOP
NOP
MRS
NOP
NOP
2
0
1
5
3
4
8
6
7
Any
NOP
Command
t
RP
t
MRD
=2 t
CK
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
RFU
0
RFU
DLL
TM
CAS Latency
BT
Burst Length
BA
0
0
1
A
n
~ A
0
MRS
EMRS
DLL
A
8
0
1
DLL Reset
No
Yes
Test Mode
A
7
0
1
mode
Normal
Test
NOP
相關PDF資料 |
PDF描述 |
|---|---|
| K4D263238M-QC50 | DIODE ZENER DUAL COMMON-CATHODE 300mW 3Vz 5mA-Izt 0.0667 0.1uA-Ir SOT-23 3K/REEL |
| K4D263238M-QC55 | 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| K4D26323QG | 128Mbit GDDR SDRAM |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| K4D263238M-QC50 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| K4D263238M-QC50000 | 制造商:Samsung SDI 功能描述: |
| K4D263238M-QC55 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| K4D263238M-QC60 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| K4D26323QG | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit GDDR SDRAM |
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