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參數(shù)資料
| 型號： | K4D263238M-QC45 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DIODE ZENER DUAL COMMON-CATHODE 300mW 39Vz 5mA-Izt 0.0513 0.1uA-Ir 29 SOT-23 3K/REEL |
| 中文描述： | 100萬x 32Bit的× 4銀行雙數(shù)據(jù)速率同步RAM的雙向數(shù)據(jù)選通和DLL |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 281K |
| 代理商： | K4D263238M-QC45 |
128M DDR SDRAM
K4D263238M
1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM
with Bi-directional Data Strobe and DLL
- 4 -
Rev. 1.3 (Aug. 2001)
The K4D263238 is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words by
32 bits, fabricated with SAMSUNG
′
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to
1.8GB/s/chip.
I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
2.5V ± 5% power supply
SSTL_2 compatible inputs/outputs
4 banks operation
MRS cycle with address key programs
-. Read latency 3,4 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
Full page burst length for sequential burst type only
Start address of the full page burst should be even
All inputs except data & DM are sampled at the positive
going edge of the system clock
Differential clock input
No Write Interrupted by Read function
GENERAL DESCRIPTION
FEATURES
Data I/O transactions on both edges of Data strobe
DLL aligns DQ and DQS transitions with Clock transition
Edge aligned data & data strobe output
Center aligned data & data strobe input
DM for write masking only
Auto & Self refresh
32ms refresh period (4K cycle)
100pin TQFP package
Maximum clock frequency up to 222MHz
Maximum data rate up to 444Mbps/pin
FOR 1M x 32Bit x 4 Bank DDR SDRAM
ORDERING INFORMATION
Part NO.
Max Freq.
Max Data Rate
Interface
Package
K4D263238M-QC45
222MHz
444Mbps/pin
SSTL_2
100 TQFP
K4D263238M-QC50
200MHz
400Mbps/pin
K4D263238M-QC55
183MHz
366Mbps/pin
K4D263238M-QC60
166MHz
333Mbps/pin
相關PDF資料 |
PDF描述 |
|---|---|
| K4D263238M-QC50 | DIODE ZENER DUAL COMMON-CATHODE 300mW 3Vz 5mA-Izt 0.0667 0.1uA-Ir SOT-23 3K/REEL |
| K4D263238M-QC55 | 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| K4D26323QG | 128Mbit GDDR SDRAM |
| K4D26323QG-GC25 | 128Mbit GDDR SDRAM |
| K4D26323QG-GC2A | 128Mbit GDDR SDRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| K4D263238M-QC50 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| K4D263238M-QC50000 | 制造商:Samsung SDI 功能描述: |
| K4D263238M-QC55 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| K4D263238M-QC60 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| K4D26323QG | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit GDDR SDRAM |
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