參數(shù)資料
型號: K4D263238M-QC45
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: DIODE ZENER DUAL COMMON-CATHODE 300mW 39Vz 5mA-Izt 0.0513 0.1uA-Ir 29 SOT-23 3K/REEL
中文描述: 100萬x 32Bit的× 4銀行雙數(shù)據(jù)速率同步RAM的雙向數(shù)據(jù)選通和DLL
文件頁數(shù): 15/19頁
文件大?。?/td> 281K
代理商: K4D263238M-QC45
128M DDR SDRAM
K4D263238M
- 15 -
Rev. 1.3 (Aug. 2001)
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case
output valid window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is defined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
tQH Timing (CL3, BL2)
1
3
4
tHP
CK, CK
DQS
DQ
CS
2
5
0
COMMAND
READA
tQH
Da0
tDQSQ(max)
tDQSQ(max)
Da1
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4D263238M-QC50 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL
K4D263238M-QC50000 制造商:Samsung SDI 功能描述:
K4D263238M-QC55 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL
K4D263238M-QC60 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL
K4D26323QG 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit GDDR SDRAM