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參數(shù)資料
| 型號： | ISPPAC80-01PI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 5/19頁 |
| 文件大小： | 342K |
| 代理商： | ISPPAC80-01PI |
Specifications
ispPAC80
5
Symbol
Dynamic Performance
tckmin
tckh
tckl
tmss
tmsh
tdis
tdih
tdozx
tdov
tdoxz
tpwp
tpwe
tpwcal1
tcalmin
tpwcal2
Parameter
Condition
Min.
Typ.
Max.
Units
Minimum Clock Period
TCK High Time
TCK Low Time
TMS Setup Time
TMS Hold Time
TDI Setup Time
TDI Hold Time
TDO Float to Valid Delay
TDO Valid Delay
TDO Valid to Float Delay
Time for a programming operation
Time for an erase operation
Time for auto-cal operation on power-up
Minimum auto-cal pulse width
Time for user initiated auto-cal operation
200
50
50
15
10
15
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
ns
ms
60
60
60
100
100
250
Executed in Run-Test/Idle
Executed in Run-Test/Idle
Automatically executed at power-up
80
80
40
Executed on rising edge of CAL
100
Timing Specifications (JTAG Interface Mode)
T
A
= 25
°
C; V
S
= +5.0V (Unless otherwise specified)
tckmin
tckh
tckl
tmss
tdis
tmsh
tdih
tdozx
tdov
tdoxz
TCK
TMS
TDI
TDO
tmss
tmss
TCK
TMS
tpwp, tpwe
*(PRGUSR/UBE executed in
Run-Test/Idle state)
CAL
(Note: CAL internally
initiated at device turn-on.)
V
OUT
= 0V
DIFF
VOUT
tpwcal1, tpwcal2
tcalmin
*Note: During device JTAG programming, analog output response will deviate from expected behavior. This is because all
configuration information is erased and then re-written as part of a normal programming cycle, momentarily changing device filter
and gain parameters. Behavior will deviate from that expected during both of these steps since the analog outputs are not clamped
during a programming cycle. During erase, a drop in the filter corner frequency and an automatic change to the 10X gain setting
can be expected (80ms minimum by specification) and will continue until bits go to there final state after a JTAG write command
is issued (less than 2ms later, though the write cycle must still be maintained for a full 80ms to achieve specified data retention).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC80-01SI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC81 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC81-01PI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC81-01SI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ispPAC-CLK5304S-01T48C | 功能描述:時鐘驅(qū)動器及分配 ISP Zero Delay Unv F an-Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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