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參數(shù)資料
| 型號： | ISPPAC30-01S |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | 在系統(tǒng)可編程模擬電路 |
| 文件頁數(shù)： | 27/30頁 |
| 文件大?。?/td> | 379K |
| 代理商： | ISPPAC30-01S |
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Lattice Semiconductor
ispPAC30 Preliminary Data Sheet
27
Test Instructions
Like data registers, the IEEE 1149.1 standard also mandates the inclusion of certain instructions. It outlines the
function of three required and six optional instructions. Any additional instructions are left exclusively for the manu-
facturer to determine. The instruction word length is not mandated other than to be a minimum of two bits, with only
the BYPASS and EXTEST instruction code patterns being speci
fi
cally called out (all ones and all zeroes respec-
tively). The ispPAC30 contains the required minimum instruction set as well as one from the optional instruction set.
In addition, there are several proprietary instructions that allow the device to be con
fi
gured and veri
fi
ed. For
ispPAC30, the instruction word length is six bits. All ispPAC30 instructions available to users are shown in Table 6.
Table 6. ispPAC30 TAP Instructions Table
BYPASS is one of the three required JTAG instructions. It selects the Bypass Register to be connected between
TDI and TDO and allows serial data to be transferred through the device without affecting the operation of the
ispPAC30. The bit code of this instruction is de
fi
ned to be all ones by the IEEE 1149.1 standard. With ispPAC30,
any instruction beginning with a one will default to BYPASS.
The JTAG required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between
TDI and TDO. The ispPAC30 has no boundary-scan register, so for compatibility it defaults to the BYPASS mode
whenever this instruction is received. The bit code for this instruction is de
fi
ned by Lattice as shown in Table 6.
The EXTEST (external test) instruction is JTAG required and would normally place the device into an external
boundary test mode while also enabling the Boundary-Scan Register to be connected between TDI and TDO.
Again, since the ispPAC30 has no boundary-scan logic, the device is put in the BYPASS mode to ensure speci
fi
ca-
tion compatibility. The bit code of this instruction is de
fi
ned by the 1149.1 standard to be all zeros.
The optional IDCODE (identi
fi
cation code) instruction is incorporated in the ispPAC30 and leaves it in its functional
mode when executed. It selects the Device Identi
fi
cation Register to be connected between TDI and TDO. The
Identi
fi
cation Register is a 32-bit shift register containing information regarding the IC manufacturer, device type
and version code (see Figure 12). Access to the Identi
fi
cation Register is immediately available, via a TAP data
Instruction
EXTEST
ADDCFG
ADDCFGQ
ADDUES
LATCHCFG
READCFG
READUES
PROGUES
PROGCFG
IDCODE
PROGESF
POWERDN
POWERUP
RELOADCFG
ERASECFG
ERASEUES
ENCAL
CFGBE
SAMPLE
BYPASS
Code
000000
000001
000010
000011
000101
000110
001010
001011
001100
001101
010001
010010
010011
010110
010111
011011
011100
011101
011110
111111
Description
External Test. Defaults to BYPASS.
Address CFG data register (112 bits).
Address CFG Quick data register (40 bits).
Address UES data register (16 bits).
Latch CFG register into control SRAM.
Read CFG from E
2
prior to ADDCFG command.
Read UES from E
2
prior to ADDUES command.
Program shift register contents into UES E
2
.
Program shift register contents into CFG E
2
.
Address Identi
fi
cation Code data register.
Program the Electronic Security Fuse bit.
Command a Power Down sequence.
Command a Power Up sequence.
Load CFG E
2
into control SRAM.
Erase the CFG/CFGQ E
2
memory.
Erase the UES E
2
memory.
Enable a Calibration sequence.
Bulk erase all E
2
memory (CFG, UES and ESF).
Sample/Preload. Default to BYPASS.
Bypass (connect TDI to TDO).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC30-01SI | 功能描述:SPLD - 簡單可編程邏輯器件 Not Upgrade Device CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC80-01PI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC80-01SI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC81 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC81-01PI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
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