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參數(shù)資料
| 型號： | ISPPAC30-01S |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | 在系統(tǒng)可編程模擬電路 |
| 文件頁數(shù)： | 19/30頁 |
| 文件大?。?/td> | 379K |
| 代理商： | ISPPAC30-01S |
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Lattice Semiconductor
ispPAC30 Preliminary Data Sheet
19
Precision Filter Con
fi
guration
Figure 5. Using the ispPAC30 as a Variable Lowpass Filter with Extended Frequency Range
Other
fi
lter frequencies are possible, in addition to the simple
fi
rst order
fi
lters available by selecting the seven avail-
able capacitors of each ispPAC30 output ampli
fi
er. The ispPAC30 can be used to implement 1st-order tunable low-
pass
fi
lters over a range of 5kHz to over 600kHz.
Figure 5 shows the circuit for doing so. This circuit operates by using MDAC2 to emulate a programmable feedback
resistor around output ampli
fi
er OA1. In this technique, the effective feedback resistance is inversely proportional to
MDAC gain. Because negative feedback is essential to maintaining a stable loop, MDAC2’s gain must be set to
only negative values.
In addition to decreasing the closed-loop bandwidth of OA1, fractional feedback gain also increases the closed
loop DC gain. This increase must be compensated for if the
fi
lter is to maintain unity gain from input to output.
Because there are two MDACs in an ispPAC30, one way to do this is to attenuate the input signal through MDAC1
by the same amount the feedback signal is attenuated by MDAC2. To maintain signal polarity, however, MDAC1
should be set to a positive gain. Deliberately mismatching the values of MDAC1 and MDAC2 also allows one to
alter the gain dynamically, providing a variable gain control feature. The following expressions can be used to esti-
mate the resulting corner frequency (F
C
) and gain, where F
CAP
is the frequency associated with the feedback.
F
C
= |F
CAP
MDAC2(n%)|
(1)
Gain = |MDAC1(n%) / MDAC2(n%)|
(2)
Note that MDAC2 (n%) must be negative, and that MDAC1 (n%) should normally be positive for the single-ended
system shown in Figure 5.
Although this technique can be used to control the corner frequency over a range of 128:1, the attenuation caused
by a very low MDAC1 setting can reduce the
fi
lter's overall signal-to-noise ratio and increase effective DC offset
and gain errors to unacceptable levels. Table 3 shows the ranges of corner frequencies that can be realized with
this technique when limiting MDAC2 settings between -10.16% and -100%.
MDAC1
MDAC2
OA1
OUT1
IN1
MDAC1 n%
MDAC2 n%
‘Integrator’ Mode
C
F
ispPAC30
V
IN
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| ISPPAC30-01SI | In-System Programmable Analog Circuit |
| ISPPAC80-01PI | In-System Programmable Analog Circuit |
| ISPPAC80-01SI | In-System Programmable Analog Circuit |
| ISPPAC81 | In-System Programmable Analog Circuit |
| ISPPAC81-01PI | In-System Programmable Analog Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC30-01SI | 功能描述:SPLD - 簡單可編程邏輯器件 Not Upgrade Device CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC80-01PI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC80-01SI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC81 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC81-01PI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
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