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參數(shù)資料
| 型號： | ISPPAC30-01S |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | 在系統(tǒng)可編程模擬電路 |
| 文件頁數(shù)： | 14/30頁 |
| 文件大?。?/td> | 379K |
| 代理商： | ISPPAC30-01S |
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Lattice Semiconductor
ispPAC30 Preliminary Data Sheet
14
Input Multiplexers
Two of the four input IA’s have dual input multiplexers in front of them. They constitute separately selectable input
paths to their respective IA’s. These paths can be con
fi
gured either by external pin, or by setting internal E
2
bits.
The control pins are named MSEL1 and MSEL2 and control the input path for IA1 and IA4, respectively. The deter-
mination of whether either of these select pins asserted high or low for choosing path “A” or “B” internally, and
whether an active pull-up or pull-down is programmed is all user-selectable from the software design interface
found in PAC-Designer. The initial con
fi
guration is called out in the pin description table in the speci
fi
cations section
of this data sheet. With multiplexer control, it is possible to bring in four different input signals and select between
them, performing selective signal conditioning on each as required. Or, one or more signals can be routed to one or
both multiplexers and thus achieve multiple signal conditioning paths for the same input, selectable by external
pins. Finally, all parameters can also be controlled and/or programmed into E
2
con
fi
guration memory in real time
using either the JTAG or SPI interface.
Internal Voltage References
Two separate voltage references (VREF1 and VREF2) are available to provide
fi
xed voltage references to the
ispPAC30’s four IA’s or two MDAC’s. Seven voltage levels are available from each VREF, and each VREF is inde-
pendently programmable from the other. Table 1 lists the binary weighted values that are available (in addition to
2.5V) and the corresponding least signi
fi
cant bit (LSB) size if this VREF value is applied to the input of either of the
MDAC’s. Since the IA’s/MDAC’s have plus and minus polarity control, VREF outputs can be added or subtracted
from other signals via the summation bus in addition to being scaled from 1 to 10 by the IA’s or attenuated in 128
steps by the MDACs. By selective combination of these various settings, a very large number of user control offset
voltages can be summed with any input signal. This is also the basis of how the ispPAC30 can be con
fi
gured as a
comparator. With the output ampli
fi
er con
fi
gured as a comparator, an unknown signal is summed with a precise ref-
erence value and an input above or below that reference level will cause a change in state of the output compara-
tor.
Table 1. Available VREF Outputs
Input MDACs
The ispPAC30 has two 8-bit (7+sign) multiplying digital to analog converters (MDAC’s) available that accept as their
reference input either external signals, internal signals or
fi
xed DC voltages (such as the internal VREFs). The mul-
tiplying DAC function means that the input is multiplied (attenuated) by a value corresponding to the code setting of
the DAC, resulting in an output that can range from 100% of the input down to a 1 LSB (least signi
fi
cant bit weight)
fraction of that value. The exact values output by the MDAC versus input code are detailed in Table 2.
The
fl
exibility of the ispPAC30 allows the MDAC’s to act as adjustable attenuators of external input signals, thereby
providing fractional or
fi
ne gain setting capability. It also means that in combination with the internal VREF’s they
can also be precision DC sources for providing
fi
xed setpoints, offsets, etc. For example, with the same input signal
applied to both an IA and MDAC, and combining both at the summing junction of one of the OA’s, an integer gain of
1 to 10 plus the fractional gain as a result of the MDAC attenuation is added together to achieve any gain value
from -11 to +11 with a resolution of greater than 0.01 throughout, for a total of more than 2,500 gain settings. See
the section on increasing MDAC resolution for more information using the MDAC’s as
fi
xed references.
VREF (V)
0.064
0.128
0.256
0.512
1.024
2.048
2.500
MDAC LSB (mV)
0.5
1.0
2.0
4.0
8.0
16.0
19.5
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC30-01SI | 功能描述:SPLD - 簡單可編程邏輯器件 Not Upgrade Device CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC80-01PI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC80-01SI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC81 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC81-01PI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
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